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Mail Archives: geda-user/2016/02/22/02:57:30

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From: geda AT psjt DOT org (Stephan =?utf-8?Q?B=C3=B6ttcher?=)
To: "Nicklas Karlsson \(nicklas.karlsson17\@gmail.com\) \[via geda-user\@delorie.com\]" <geda-user AT delorie DOT com>
Subject: Re: [geda-user] pcb import schematic crash, parantheses in netname
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Date: Mon, 22 Feb 2016 08:56:37 +0100
In-Reply-To: <20160222074947.0f31d0ee70fbc56e2b4123ad@gmail.com> (Nicklas
Karlsson's message of "Mon, 22 Feb 2016 07:49:47 +0100")
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"Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via
geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> writes:

>> >> What to you mean by dodge them in the back end?
>> >
>> > There’s code in gnetlist that allows a back end to alias refdes
>> > and netname values that violate its rules.
>> 
>> Rather than rewriting them, it would be better to just trap them and
>> give a reasonable error message.  This would be less good than a
>> gschem that catches them immediately, but much better than the current
>> situation. ...
>
> To trap them and give a resonable error message would be the correct
> path. They could be catched in gschem but it will not work if there
> are differences between back ends so then running gnetlist would be
> the correct point.

The gnetlist backend needs to know the synatx and semantics of the
output format it produces.  The syntax spec includes quoting needs and
methods.  It needs to implement them.

The receiver may add additional restrictions to the semantics, if
needed, like allowed characters in refdes, and throw warnings or error
messages when those are violated.  It does not make a lot of sense to
implement the list of disallowed characters twice.  

There must not be seqfaults.

It does not make a lot of sense to restrict the allowed char set too
much. Maybe somebody wants to use verilog to generate a PCB netlist,
with netnames like \top.core(3,56).x[0] and pin names like \d[4] .

As for UTF-8, all my resistor values include the unit Ω, and a lot of
capacitors use µF.

-- 
Stephan

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