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Date: Tue, 26 Jan 2016 14:58:45 -0500
Message-ID: <CANEvwqjrvyWVDVdaFdVNPKjeXBqgZTgzDNb8YStgcKQ4HARM2Q@mail.gmail.com>
Subject: Re: [geda-user] [pcb] poll: burried/blind vias vs. pcb and pcb-rnd
(How ?)
From: "Marvin Dickens (mpdickens AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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--001a114ab048f9f134052a421c48
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I give up. With that said, for the record, I cannot afford to have a custom
ASIC
manufactured, but my client(s) can and do when an FPGA will not fulfill
design
requirements. Further, my point was all three types of property -medium to
large
FPGA's, ASICS's and BGA's require blind/buried vias. In addition, large
SOIC's,
are becoming cheap/popular for low production run designs benefit greatly
from
B/B vias - Places like Adafruit are beginning to pick up large SOIC designs
not to mention
they have published small FPGA designs for years. In fact, if your read the
blogs
at adafruit, the small FPGA's they have been using have "hit the wall" so
speak.
Even so, some of the adafuit designs already utilize B/B Vias.

So, there it is - Hobby/educational stuff using B/B via's...

Regards

Marvin

On Tue, Jan 26, 2016 at 1:04 PM, DJ Delorie <dj AT delorie DOT com> wrote:

>
> > In this day and age to say blind/buried vias are not needed is
> ridiculous.
> > The fact is ANY design that requires even one FPGA, custom ASIC or
> > medium to large BGA needs blind/buried vias.
> >
> > This is factual and is easy vetted.
>
> If you can afford a custom ASIC, you can afford a top-end EDA package,
> and a FAB that supports high-end features.  Frankly, PCB is not a
> high-end package and custom ASIC users are not our target audience.
>
> I can't afford any of that tech.  Heck, I can barely afford 4-layer
> boards with 6/6 rules.  There's a huge community of designers that
> can't (or won't) afford high tech features in their boards.
>
> So you can say "this is factual" but it's not.  It may be a
> requirement for a subset of our potential user base, but it's not
> ridiculous to assume that many people just aren't going to use them.
> Until we decide to support that tech, we're simply targetting the
> "many people" who don't need them.
>

--001a114ab048f9f134052a421c48
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<div dir=3D"ltr">I give up. With that said, for the record, I cannot afford=
 to have a custom ASIC=C2=A0<div>manufactured, but my client(s) can and do =
when an FPGA will not fulfill design</div><div>requirements. Further, my po=
int was all three types of property -medium to large</div><div>FPGA&#39;s, =
ASICS&#39;s and BGA&#39;s require blind/buried vias. In addition, large SOI=
C&#39;s,</div><div>are becoming cheap/popular for low production run design=
s benefit greatly from=C2=A0</div><div>B/B vias - Places like Adafruit are =
beginning to pick up large SOIC designs not to mention</div><div>they have =
published small FPGA designs for years. In fact, if your read the blogs</di=
v><div>at adafruit, the small FPGA&#39;s they have been using have &quot;hi=
t the wall&quot; so speak.</div><div>Even so, some of the adafuit designs a=
lready utilize B/B Vias.</div><div><br></div><div>So, there it is - Hobby/e=
ducational stuff using B/B via&#39;s...=C2=A0</div><div><br></div><div>Rega=
rds</div><div><br></div><div>Marvin</div></div><div class=3D"gmail_extra"><=
br><div class=3D"gmail_quote">On Tue, Jan 26, 2016 at 1:04 PM, DJ Delorie <=
span dir=3D"ltr">&lt;<a href=3D"mailto:dj AT delorie DOT com" target=3D"_blank">dj=
@delorie.com</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quote" sty=
le=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span =
class=3D""><br>
&gt; In this day and age to say blind/buried vias are not needed is ridicul=
ous.<br>
&gt; The fact is ANY design that requires even one FPGA, custom ASIC or<br>
&gt; medium to large BGA needs blind/buried vias.<br>
&gt;<br>
&gt; This is factual and is easy vetted.<br>
<br>
</span>If you can afford a custom ASIC, you can afford a top-end EDA packag=
e,<br>
and a FAB that supports high-end features.=C2=A0 Frankly, PCB is not a<br>
high-end package and custom ASIC users are not our target audience.<br>
<br>
I can&#39;t afford any of that tech.=C2=A0 Heck, I can barely afford 4-laye=
r<br>
boards with 6/6 rules.=C2=A0 There&#39;s a huge community of designers that=
<br>
can&#39;t (or won&#39;t) afford high tech features in their boards.<br>
<br>
So you can say &quot;this is factual&quot; but it&#39;s not.=C2=A0 It may b=
e a<br>
requirement for a subset of our potential user base, but it&#39;s not<br>
ridiculous to assume that many people just aren&#39;t going to use them.<br=
>
Until we decide to support that tech, we&#39;re simply targetting the<br>
&quot;many people&quot; who don&#39;t need them.<br>
</blockquote></div><br></div>

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