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Date: Tue, 26 Jan 2016 12:30:18 -0500
Message-ID: <CANEvwqgs3YFnt7m8mA1DN6X2KdWbyr4zpXCVH321vDo1f7CyxA@mail.gmail.com>
Subject: Re: [geda-user] [pcb] poll: burried/blind vias vs. pcb and pcb-rnd
(How ?)
From: "Marvin Dickens (mpdickens AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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In this day and age to say blind/buried vias are not needed is ridiculous.
The fact is ANY design that requires even one FPGA, custom ASIC or
medium to large BGA needs blind/buried vias.

This is factual and is easy vetted.

Regards

Marvin

On Tue, Jan 26, 2016 at 6:47 AM, Nicklas Karlsson (
nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com] <
geda-user AT delorie DOT com> wrote:

> > The conclusion from the poll is also that there is no strong demand to
> > support/provide windows binaries.
> >
> > However IMO blind/burried vias and windows availability are essential to
> > attract new users, I do hope that that broader scope is picked-up by
> > main stream pcb.
> >
> > Cheers,
> > Robert.
>
> Even though it should not be implemented right now it could be good with a
> discussion how it ideally should work.
>
> An essential question is how it should be defined in pcb. On a higher
> level I could see a choice between the layers in form of board/laminate it
> make hole in or to define between which layers it should be
> drilled/connected. I could identify three different implementation methods
> immediately:
>   1. Define on which layers there should be a hole.
>   2. Define between which copper layer via should be.
>   3. In principal define which layers should be connected by connecting on
> the particular layer.
>
> Number (3.) may be good because layers needed to span will be implicitly
> given by on which layer via is used but there are a few problems:
>   1. Then there are two different via above each other that do not
> connect, how to handle for the user?
>   2. Snap to via, how to choose between bypass and connect?
> Then it is implicitly given which layer need to connect I guess the
> minimum possible layers to span for the current design could be chosen
> automatically for the most common cases although it would still be possible
> to implement override if needed.
>
> Nicklas Karlsson
>

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<div dir=3D"ltr">In this day and age to say blind/buried vias are not neede=
d is ridiculous.<div>The fact is ANY design that requires even one FPGA, cu=
stom ASIC or</div><div>medium to large BGA needs blind/buried vias.</div><d=
iv><br></div><div>This is factual and is easy vetted.</div><div><br></div><=
div>Regards</div><div><br></div><div>Marvin</div></div><div class=3D"gmail_=
extra"><br><div class=3D"gmail_quote">On Tue, Jan 26, 2016 at 6:47 AM, Nick=
las Karlsson (<a href=3D"mailto:nicklas DOT karlsson17 AT gmail DOT com">nicklas.karls=
son17 AT gmail DOT com</a>) [via <a href=3D"mailto:geda-user AT delorie DOT com">geda-use=
r AT delorie DOT com</a>] <span dir=3D"ltr">&lt;<a href=3D"mailto:geda-user AT delori=
e.com" target=3D"_blank">geda-user AT delorie DOT com</a>&gt;</span> wrote:<br><bl=
ockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #=
ccc solid;padding-left:1ex">&gt; The conclusion from the poll is also that =
there is no strong demand to<br>
&gt; support/provide windows binaries.<br>
&gt;<br>
&gt; However IMO blind/burried vias and windows availability are essential =
to<br>
&gt; attract new users, I do hope that that broader scope is picked-up by<b=
r>
&gt; main stream pcb.<br>
&gt;<br>
&gt; Cheers,<br>
&gt; Robert.<br>
<br>
Even though it should not be implemented right now it could be good with a =
discussion how it ideally should work.<br>
<br>
An essential question is how it should be defined in pcb. On a higher level=
 I could see a choice between the layers in form of board/laminate it make =
hole in or to define between which layers it should be drilled/connected. I=
 could identify three different implementation methods immediately:<br>
=C2=A0 1. Define on which layers there should be a hole.<br>
=C2=A0 2. Define between which copper layer via should be.<br>
=C2=A0 3. In principal define which layers should be connected by connectin=
g on the particular layer.<br>
<br>
Number (3.) may be good because layers needed to span will be implicitly gi=
ven by on which layer via is used but there are a few problems:<br>
=C2=A0 1. Then there are two different via above each other that do not con=
nect, how to handle for the user?<br>
=C2=A0 2. Snap to via, how to choose between bypass and connect?<br>
Then it is implicitly given which layer need to connect I guess the minimum=
 possible layers to span for the current design could be chosen automatical=
ly for the most common cases although it would still be possible to impleme=
nt override if needed.<br>
<span class=3D"HOEnZb"><font color=3D"#888888"><br>
Nicklas Karlsson<br>
</font></span></blockquote></div><br></div>

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