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Mail Archives: geda-user/2016/01/10/11:57:53

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Subject: Re: [geda-user] Primitive electrical types [WAS: Re: first attempt at
bus support in gnetlist for pcb]
To: geda-user AT delorie DOT com
References: <CAJXU7q8edycnyhZbZ7+M3q6HA13U4Tr5R9M7KAG59HVpH2+cMg AT mail DOT gmail DOT com>
From: John Griessen <john AT ecosensory DOT com>
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Date: Sun, 10 Jan 2016 10:57:19 -0600
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On 01/09/2016 06:55 AM, Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com] wrote:
> Pins and nets have different semantics regarding connection points - for one example. (One end only, vs. either end - plus
> end-point to lands-on-line connections.)  To me, this implies there should be different types internally, even if they are
> notionally sub-classes.

The subject of types got me thinking of keeping it simple.  There are packaged types and layout group types and the rest is simply 
materials attribs of something-on-insulator.   I think the easiest way forward is layers model something-on-insulator, and the 
something can be on one side only, and that side can be oriented up or down.

With just the above, you can say:
silk on top is part of the topmost layer of something-on-insulator with something on the upside.
middle layers are something-on-insulator with something on the upside.
silk on bottom is part of the bottommost layer of something-on-insulator with something on the bottom side.


The thickness of the bottommost insulating layer might be zero -- that's OK.  The silk has silk attrib material properties that 
give it a thickness.

The above is enough to derive a complete 3D result model including curvy overlapping of painted on layers that dry,
etching, photosensitive layers, etc.  You could get from there to STEP later, (or never and still use STEP export heuristically)

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