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	Thu, 15 Oct 2015 13:13:36 -0700 (PDT)
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Date:	Thu, 15 Oct 2015 16:13:36 -0400
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Subject:	Re: [geda-user] Design rule, suitable attributes at least for current
From:	"Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On Thu, Oct 15, 2015 at 1:16 PM, Nicklas Karlsson
(nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]
<geda-user AT delorie DOT com> wrote:
>> > There have been discussions lately about attributes on pins and nets. On commercial tools I have used it is usually possible to specify minimum, standard and maximum value for width of traces.
>> >
>> > If current is specified instead of width it would be possible to use a mapping of currents to trace width which may be different for different layers and I actually think this approach would actually outperform the commercial tools.
>> >
>> > If current range which will be negative for opposite direction is specified for pins it would be possible for tools automatically calculate current range for all segments in circuit. Then maximum rms value have been calculated this could be used to automatically map currents to trace widths.
>>
>> You could write a backend to do that after we fix things so that nets
>> are not flattened but some things need to be mentioned.
>>
>> While I like the idea in concept there are issues. For starters you
>> would have to specify the copper thickness and if the trace was going
>> to have solder mask removed and solder on it. Then there are the
>> implications of ambient temperature the effect of which changes with
>> airflow. When you get into some aspects of this it is possible to hit
>> a higher level of complexity then you might expect from looking at the
>> crude trace width calculators laying around the net most of which are
>> really only good for DC (or fixed RMS AC), with no airflow, a stable
>> ambient temperature and so on. This is why the other vendors let the
>> user do the math. There are also times when trace thickness is not
>> about current carrying capacity but other issues of signal integrity
>> from parasitics, heat dissipation (ex LDO's using trace as heatsink),
>> and etc. Meaning that you would want to be able to mix the two methods
>> of specifying.
>>
>> I am not saying you should not pursue this, you are on the right
>> track. I am just saying that there is more math involved and
>> interdependencies with the rest of the layout that are not all
>> apparent on the schematic.
>>
>> > Regards Nicklas Karlsson
>>
>>
>>
>> --
>> Home
>> http://evanfoss.googlepages.com/
>> Work
>> http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/
>
> Yes there are special cases in particular for high frequencies and manual intervention must be possible but I think automatic assignment of track width from maximum RMS current will cover the most basic cases. If mapping window is graphic and have some documentation about temperature rise calculations or maybe link this kind of documentation it would help. I still have not had time to write a single row but I will try to.

Keep in mind trace resistance grows with length which also changes
this. Yes for high frequencies this matters but it also gets complex
in other domains.

"Mapping window"? Are you picturing some kind of wizard to calculate
trace width in pcb?

> Nicklas Karlsson



-- 
Home
http://evanfoss.googlepages.com/
Work
http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/

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