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	Mon, 12 Oct 2015 20:56:10 -0700 (PDT)
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Date:	Tue, 13 Oct 2015 03:56:10 +0000
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Subject:	Re: [geda-user] A lesson from gnet-makefile
From:	"Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On Mon, Oct 12, 2015 at 11:04 PM, John Doty <jpd AT noqsi DOT com> wrote:
>
> On Oct 12, 2015, at 1:42 PM, Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:
>
>>
>> This is related to what we were talking about earlier here.
>> https://bugs.launchpad.net/geda/+bug/698771
>
> That’s about pcb. I have little interest in pcb-specific discussions.

Ok at my stuff at the end. I posted a concept of what I thought it
should look like in gschem. I would like to revise part of it. You
have a point about pins but I feel like it would get very hard to read
if all those net attributes were stacked onto the symbols instead of
the nets. Plus it is kind of bending the way we have always made
things direct honest relations from gschem to gnetlist output.

>> (I have since realized there are things in the example sch file that
>> could use tweeking)
>>
>> I also had some off list talk with John Griessen who was looking even
>> farther out than we are (RF layout and verilog-ams).
>> The output format for gnetlist is an interesting question.
>
> To start, we should think about how to represent the additional data in a schematic. If there are downstream tools that can handle this data, the way they encode it may be of interest. Generally, though, this is a gschem issue: how do we devise symbols and attributes that represent what we want? Do we need changes in the core (I hope not)? Translation to the various layout and simulation tools is then a job for gnetlist or xorn. Pcb, having no mechanism to do anything with this data, isn't terribly relevant at present.

Well there needs to be something that works like s_conn and it's
partners in gnetlist that walks the list mapping the nets but with
this added metadata.

> What we need is knowledge of layout programs that *can* handle this sort of extra data. Without tools to export to, what good is it? Finding out this information seems difficult.

Good points although I would be happy to just have notations in pcb in
the short term. We should also keep back notation of this in mind
since a lot of layout architecture can change after you go to your pcb
program.

> John Doty              Noqsi Aerospace, Ltd.
> http://www.noqsi.com/
> jpd AT noqsi DOT com
>
>



-- 
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http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/

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