Mail Archives: geda-user/2015/06/09/16:48:15
Do you have examples of that inconsistency? Just checked with the JEDEC
standard (see below) and also checked a datasheet from Xilinx and LT
each, and they all agree. I checked these:
www.jedec.org/sites/default/files/docs/SPP-020A.pdf
http://www.linear.com/docs/46540
www.xilinx.com/support/documentation/package_specs/ft256.pdf
There seems to have been some ambiguity with the JEDEC standard (JEP95
SPP-010) regarding this numbering, which was clarified in JEP95
SPP-020A.
The standard (SPP-020A) states that when viewing the package from top in
the as-mounted orientation with A1 at the top left corner (i.e. same as
looking at an unpopulated PCB footprint) the columns are enumerated
1,2,3 left-to-right and the rows are enumerated A,B,C top-to-bottom.
But to cite the background from SPP-020A:
"The numbering practice for grid array packages has been clearly defined
for square packages in JEP95,
Section 3, SPP-010. The application of this practice to rectangular
array packages is ambiguous and has led to inconsistency in the
numbering shown in JEDEC outlines."
/Jonatan
On tis, 2015-06-09 at 13:21 -0700, Edward Hennessy
(ehennes AT sbcglobal DOT net) wrote:
> After looking around, I've found two different pin numbering schemes. (Could be more.)
>
> When rotating the package so pin A1 is in the upper left, one scheme uses letters for the rows and numbers for the columns. The other uses numbers for the rows and letters for the columns.
>
> Examining datasheets, Linear uses one scheme, and Xilinx uses another.
>
> I need to update my footprint generator.
>
> Cheers,
> Ed
>
> Sent from my iPhone
>
> > On Jun 9, 2015, at 9:11 AM, DJ Delorie <dj AT delorie DOT com> wrote:
> >
> >
> > I wonder if BGAs have the transistor problem... that the tool is
> > correct for some BGAs and wrong for others, and if we fix it it will
> > be correct for some BGAs and wrong for others.
>
--
Jonatan Ã…kerlind
+46702002897
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