Mail Archives: geda-user/2014/10/29/11:17:42
On 10/28/2014 02:07 PM, Abhijit Kshirsagar wrote:
> Yes we use gschem as is. Graphical diffs (and well written commit
> mesages) are usually enough - we have rarely needed look closely at
> the diff of the sch.
OK. How do you get the graphical diff? Have you come up with an automated way?
> Plus we use multipage and hierarchical schematics to separate out
> logical entities for the most part, so that helps a lot too. IMO these
> would give a cleaner approach than having to text-diff the sch file at
> all...
Oh, I see now. Have collaborators work on separate pages with
separations that keep them away from each other by design.
Sounds good.
On 10/28/2014 05:07 PM, Britton Kerin wrote:>
+1 +1 +1. The question is, what can we do to get to the point where
hierarchical schematics are truly portable and sharable?
I know I make these same noises often,
sorry, but I to admit I have no real idea how to start on this.
I get the feeling no one else has a realistic
> idea either.
To me, it needs the approach of chip design tools where
verilog or another schematic can be inside any module and
busses connect properly terminated to a module port
that is not limited to being a single conductor, but
can be a name like DACin[0:9]. Coding it seems hard, but
maybe possible. Agreeing on what to do is, uh... harder,
and mostly just waiting
on someone to do it and announce as a fait accompli...
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