Mail Archives: geda-user/2014/06/28/21:18:49
On Sat, 2014-06-28 at 12:14 -0400, DJ Delorie wrote:
> > A question still unclear in my head.. should we define a pad stack
> > which has the relevant properties / pad geometry, and call that out
> > repeatedly, OR.. should we continue in PCB's current approach, and
> > have every single via entity describe these aspects individually.
>
> I've used both types of tools, and IMHO it's better to have a "canned"
> geometry that you can reference, as well as making exceptions.
> Sketchup has a good implementation of this, but lacks a way of finding
> all features that are exceptions.
Is this in favour of, or against indirecting through reference to a
separately defined padstack? (We could still choose to copy-on-write, or
edit-all when modifying vias / pads).
Would a pad-stack definition be explicit for the board stack-up in use,
or would it more usefully read something like:
TOP PASTEMASK LAYER : Round 2.0mm
TOP SOLDERMASK LAYER : Round 2.2mm
TOP (or START?) LAYER : Round 2.0mm Clear Round 2.4mm
INTERMEDIATE LAYER : Round 2.1mm Clear Round 2.5mm
BOTTOM (or END?) LAYER : Round 2.0mm Clear Round 2.4mm
BOTTOM SOLDERMASK LAYER : Round 2.2mm
BOTTOM PASTEMASK LAYER : Round 2.0mm
> > I really wish PCB didn't have the concept of layer groups to
> > complicate this. They are REALLY unhelpful. Plain _layers_, defined
> > to be in a particular numerical order through the board stack-up
> > would be a MUCH easier model to use.
>
> We'd still need a way to have one layer be composed of different
> things-that-become-gerbers. An obvious example of this is the
> top/bottom layers, which have copper, mask, paste, and silk.
The grouping is only really to allow footprint placement, IE.. that the
pads, copper and silkscreen items called out within the footprint file
go into the correct layers when we place things.
"top" is not actually a layer per-se, nor would all of the above
physical layers be considered at the same Z-coordinate of the board.
I know DJ knows the workings, but for others reading, my assessment is
that the only reason we include top-silk in the group with the top
copper layer so we can IDENTIFY the top copper layer. (Likewise with the
bottom layer).
The top and bottom silk layers have defined numerical offsets in the
layer data-structure... whereas, the copper layers can be in any
non-physical order (and indeed, there can be more than one, additively
combined to produce the final layer image).
The "paste" (and "mask" - git HEAD), layers currently don't actually
exist within PCB, certainly not in the layer groups structure. The
rendering and export routines construct them on the fly using the
attributes and properties of other object like pins, pads and vias.
The additive combination of multiple underlying layers is a nuisance
from a code point of view.. it means we need to combine these various
data-sources to check for connectivity, and it means some operations can
be slowed - as the spatial indexes are kept per-layer, not per group.
IMO, although the history pre-dates my involvement, PCB's layer groups
only really exist as a substitute for being able to tag objects by
class, or property.
As sub-layers within a group cannot be turned on/off individually, and
are output together for export, the functionality remaining only boils
down to being able to distinctly colour certain objects. (And perhaps
separate them easily - as you can temporarily reassign the layer groups
in order to separate a sub-layer, and keep them separate within the PCB
file.).
> > then the board stack-up of is considered to be the numerical
> > sequence (either ascending or descending) of these two layer-groups
> > and any in between.
>
> Photo mode does this too, and OSH Park interprets PCB layouts this
> way.
Does photo mode use anything other than the outer-layers though?
--
Peter Clifton <peter DOT clifton AT clifton-electronics DOT co DOT uk>
Clifton Electronics
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