Mail Archives: geda-user/2014/06/28/10:08:29
On Fri, 2014-06-27 at 21:55 -0600, Bdale Garbee wrote:
> Peter Clifton <pcjc2 AT cam DOT ac DOT uk> writes:
>
> > On Fri, 2014-06-27 at 15:14 -0600, Bdale Garbee wrote:
> >
> >> Real-world blind and buried vias always connect a range of layers from N
> >> to M. The tricky bit in my experience in large-layer-count boards was
> >> always when there were multiple buried vias with the same X-Y
> >> coordinate. In other words, something like layers 2-3 and 6-7 connected
> >> in an 8-layer board.
> >
> > Hmm, turns out there is such a thing as a layer1-3 skip via.
>
> Interesting, but it's hard for me to see how it's practically different
> From a layer 1-3 via with a keep-out around the via on layer 2? The
> question I guess is what info does the fab need to make such a
> structure? From a design standpoint, it seems to be mostly about
> allowing different annular ring diameters per layer?
It just suggests to me that there are complexities to all this. I'm
still not sure if you can construct a direct layer 1-3 via without a
skip, for example. (I guess it depends on whether the laser process
involved can cut through the pad on layer 2.)
_____ _______
__\ /__
___\_/___
_________________
Of course - the pad on layer two might need a hole in it to allow the
laser to cut the HDI dielectric underneath rather than having to ablate
the copper.
High speed design requires removing unused pads from vias, so I guess we
need to be able to control pad generation on vias anyway. I guess it
will just have to be the board vendor's DRC (perhaps eventually our DRC)
which untangles whether a design is manufacturable.
Rather than model vias from-to layers, we could model any-layer vias,
and post-process out the groups of from-to files.
A question still unclear in my head.. should we define a pad stack which
has the relevant properties / pad geometry, and call that out
repeatedly, OR.. should we continue in PCB's current approach, and have
every single via entity describe these aspects individually.
I really wish PCB didn't have the concept of layer groups to complicate
this. They are REALLY unhelpful. Plain _layers_, defined to be in a
particular numerical order through the board stack-up would be a MUCH
easier model to use.
For the 3D work, I have adopted the convention that top and bottom
layers are identified (as usual, by looking which group their silk
layers are combined with), then the board stack-up of is considered to
be the numerical sequence (either ascending or descending) of these two
layer-groups and any in between. Any layer groups outside this range are
not considered part of the stack-up layers, so are not drawn in 3D. They
COULD be considered non-copper if so desired - not that I currently use
this rule.
--
Peter Clifton <peter DOT clifton AT clifton-electronics DOT co DOT uk>
Clifton Electronics
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