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Subject:	Re: [geda-user] Include VHDL code in sym file?
From:	John Doty <jpd AT noqsi DOT com>
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Date:	Sat, 17 Aug 2013 10:10:37 -0600
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On Aug 17, 2013, at 9:29 AM, myken wrote:

> Hello all,
> 
> Is it possible to include VHDL code in the sym file or attach it through an external file?

Sure. Just stick it in an attribute.

> I like to use gschem to make a top level design and include some VHDL blocks. After that I will generate the VHDL code through gnetlist. It would be nice if I could include some VHDL code which will also be include in the code generated by gnetlist.

I don't know how the vhdl back end for gnetlist works. However, my experimental SPICE back end at https://github.com/noqsi/gnet-spice-noqsi processes symbol attributes (spice-prototype and file) as well as toplevel attributes (spice-prolog and spice-epilog) to create arbitrary SPICE code output. It processes these through a simple macro expander, so they can refer to other attributes and net/pin connections. This might be an approach you could use for VHDL as well.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com

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