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Date:	Sat, 17 Aug 2013 17:29:53 +0200
From:	myken <myken AT iae DOT nl>
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To:	geda-user AT delorie DOT com
Subject:	[geda-user] Include VHDL code in sym file?
Reply-To:	geda-user AT delorie DOT com

Hello all,

Is it possible to include VHDL code in the sym file or attach it through 
an external file?
I like to use gschem to make a top level design and include some VHDL 
blocks. After that I will generate the VHDL code through gnetlist. It 
would be nice if I could include some VHDL code which will also be 
include in the code generated by gnetlist.

Thanks,
Best regards,
Robert

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