Mail Archives: geda-user/2013/01/17/01:23:14

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From: Abhijit Kshirsagar <abhijit86k AT gmail DOT com>
Date: Thu, 17 Jan 2013 11:51:49 +0530
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Subject: Re: [geda-user] gnetlist hierarchy uref order setting
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>Interesting. Stuart seems not to have implemented refdes "munging" for all of the components he lists at

So does that count as a bug?

> Put (hierarchy-traversal "disabled") in your gnetlistrc. Then I netlist subcircuits separately and
> let SPICE do the hierarchy expansion. See

I've looked through this - and it seems to be the same as the RF
example that ships with the gEDA distribution.
As i understand, I need to generate the cir files from the
sub-schematics first, then netlist the top level schematics.

Do most people use something like a makefile, when systems become
large? Is there a makefile generator out there?

I was hoping to have everything (including the SPICE simulation
commands) in schematics only - so the end user only needs to keep
gSCHEM open and navigate the hierarchy to see the entire design.


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