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Mail Archives: geda-user/2012/12/15/08:15:07

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Sender: Richard Barlow <skkinny AT gmail DOT com>
Message-ID: <1355577174.24123.61.camel@thinkpad.richardbarlow.co.uk>
Subject: Re: [geda-user] Find rat lines
From: Richard Barlow <richard AT richardbarlow DOT co DOT uk>
To: geda-user AT delorie DOT com
Date: Sat, 15 Dec 2012 13:12:54 +0000
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On Fri, 2012-12-14 at 10:29 +0100, Levente wrote:
> I lost track of this thread, but I have an idea. I've seen this
> implementation in Zuzken CR5000 Board designer. Each copper object had
> an attribute called "net". When you place a track you could click on
> an object to connect to. This way, there is no need to do any graphs,
> etc. Just compare touching copper objects net attribute. If it is not
> the same emit warning.

A few weeks ago I had to layout a board using Eagle, due to the project
already using Eagle. From my experience Eagle uses this method and I
found it to be extremely annoying to use. For the most part it was fine,
but the one thing that was very hard to do was place vias and then route
traces to/from them. It's fine if you're placing a trace and switch
layers; Eagle places a via and all the net attributes are correct.
However this isn't that great a work-flow if you're laying out a very
dense board, where you have to jiggle things around to get an wide bus
onto another layer. Eagle complains continuously about nets being
shorted.

I also encountered other annoying situations caused by this manual
assignment of net attributes to everything, where I found myself
effectively managing the EDA's state for it, rather than getting on with
the task in hand.

I find PCB's method of tracking connectivity to be less constraining and
allows for more varied work-flows. It's also closer to reality in that
ultimately what matters is the actual connection between things, the
copper doesn't care what net it belongs to. The only bad thing with
PCB's method is the highlighting of shorts and it seems that it should
be possible to preserve PCB's current behaviour while vastly improving
this using some graph theory. If at all possible I think we should
strive to keep the notion of copper being 'free' in PCB.

Rich

P.S. This was my first time using Eagle for layout, so I'm sure I wasn't
necessarily using it correctly. However, after much searching on the
internet, it seems there isn't any nice way around the
place-via-place-trace problem.

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