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From:	"karl AT aspodata DOT se [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] PCB silk layer image script
In-reply-to:	<4587f76d-f3ff-e682-7d96-48fdc2d91aee@linetec.nl>
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Comments:	In-reply-to "Richard Rasker (rasker AT linetec DOT nl) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
	message dated "Tue, 03 Oct 2023 09:15:26 +0200."
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Date:	Tue, 3 Oct 2023 10:11:32 +0200 (CEST)
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Richard Rasker:
> Op 03-10-2023 om 00:00 schreef karl AT aspodata DOT se [via geda-user AT delorie DOT com]:
> > Richard Rasker:
> > ...
> >> Anyway, thanks for the help, and I hope other people find this script
> >> useful as well. Of course I'm always open to bug reports and suggestions
> >> for improvements.
> >   Very nice.
> >
> > Layer(6 "top silk") doesn't work here, I need
> > Layer(5 "top silk") for it to show in pcb.
> 
> Is this when importing the logo file into a 2-layer pcb project using 
> File -> Load layout to buffer?

 No, it is when I do
pcb TestLogo.pcb &
 With 6, I don't see anything but the outline, with 5 I see the logo.

Regards,
/Karl Hammar

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