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| 2023 07:38:48 -0800 (PST) | |
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| References: | <e142bdaf-597f-6219-5653-993cf530a50a AT linetec DOT nl> |
| <40bb8153-a4f9-b79c-b4db-d5ed94516e67 AT grinsen-ohne-katze DOT de> | |
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| From: | "Chad Parker (parker DOT charles AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
| Date: | Sun, 5 Mar 2023 10:38:37 -0500 |
| Message-ID: | <CAJZxidDyCdTaMP6DKwzGfynDyy8iNmbywy71NHFh5KocRApPhg@mail.gmail.com> |
| Subject: | Re: [geda-user] Connecting pads directly to polygons (was: Strange |
| errors importing gschem into PCB) | |
| To: | geda-user AT delorie DOT com |
| Cc: | Bert Timmerman <ljh4timm AT xs4all DOT nl> |
| Reply-To: | geda-user AT delorie DOT com |
--00000000000077c75c05f628f9ef Content-Type: text/plain; charset="UTF-8" The correct way to do it is to use thermals or traces to connect pads to planes, not to set the clearance to zero. On Sun, Mar 5, 2023, 10:18 Roland Lutz <rlutz AT hedmen DOT org> wrote: > On Sun, 5 Mar 2023, Richard Rasker (rasker AT linetec DOT nl) [via > geda-user AT delorie DOT com] wrote: > > Op 04-03-2023 om 23:24 schreef Roland Lutz: > >> This patch should fix the issue: > >> > https://github.com/rlutz/geda-gaf/commit/9b74190843364861b9fc6841d927dc2747d63488 > > > > Thank you for this quick fix! This indeed solves the problems with > > unconnected duplicate pins. > > Thank you for testing the patch! > > > > Final question: is there a way to connect pads directly to polygons > > without the DRC warning "Pad with insufficient clearance inside > > polygon"? Lines can be connected to polygons using 'J(oin)', but that > > doesn't work for pads. > > > > In some older designs with lots of thermal and high-current pads I now > > get almost a hundred of these DRC warnings, increasing the risk of > > overlooking any new, real DRC issues. I guess I could trace the outline > > of e.g. TO252 tabs, using 'J' to connect them to the surrounding > > polygon, but that feels like a bit of a messy kludge. > > > > Maybe it is possible to prevent this Design Rule from being applied when > > the clearance is actually zero? Because I'd say that unintentional > > shorts are already caught by the connection check, and that this rule > > check is only needed to locate non-zero distances that are too small. > > I'm not too familiar with PCB. Maybe Bert can help? > > --00000000000077c75c05f628f9ef Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable <div dir=3D"auto">The correct way to do it is to use thermals or traces to = connect pads to planes, not to set the clearance to zero.</div><br><div cla= ss=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmail_attr">On Sun, Mar 5, 202= 3, 10:18 Roland Lutz <<a href=3D"mailto:rlutz AT hedmen DOT org">rlutz AT hedmen DOT o= rg</a>> wrote:<br></div><blockquote class=3D"gmail_quote" style=3D"margi= n:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On Sun, 5 Mar 202= 3, Richard Rasker (<a href=3D"mailto:rasker AT linetec DOT nl" target=3D"_blank" r= el=3D"noreferrer">rasker AT linetec DOT nl</a>) [via <br> <a href=3D"mailto:geda-user AT delorie DOT com" target=3D"_blank" rel=3D"noreferre= r">geda-user AT delorie DOT com</a>] wrote:<br> > Op 04-03-2023 om 23:24 schreef Roland Lutz:<br> >> This patch should fix the issue:<br> >> <a href=3D"https://github.com/rlutz/geda-gaf/commit/9b741908433648= 61b9fc6841d927dc2747d63488" rel=3D"noreferrer noreferrer" target=3D"_blank"= >https://github.com/rlutz/geda-gaf/commit/9b74190843364861b9fc6841d927dc274= 7d63488</a> <br> ><br> > Thank you for this quick fix! This indeed solves the problems with <br= > > unconnected duplicate pins.<br> <br> Thank you for testing the patch!<br> <br> <br> > Final question: is there a way to connect pads directly to polygons <b= r> > without the DRC warning "Pad with insufficient clearance inside <= br> > polygon"? Lines can be connected to polygons using 'J(oin)= 9;, but that <br> > doesn't work for pads.<br> ><br> > In some older designs with lots of thermal and high-current pads I now= <br> > get almost a hundred of these DRC warnings, increasing the risk of <br= > > overlooking any new, real DRC issues. I guess I could trace the outlin= e <br> > of e.g. TO252 tabs, using 'J' to connect them to the surroundi= ng <br> > polygon, but that feels like a bit of a messy kludge.<br> ><br> > Maybe it is possible to prevent this Design Rule from being applied wh= en <br> > the clearance is actually zero? Because I'd say that unintentional= <br> > shorts are already caught by the connection check, and that this rule = <br> > check is only needed to locate non-zero distances that are too small.<= br> <br> I'm not too familiar with PCB.=C2=A0 Maybe Bert can help?<br> <br> </blockquote></div> --00000000000077c75c05f628f9ef--
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