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From: | "karl AT aspodata DOT se [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
To: | geda-user AT delorie DOT com |
Subject: | Re: [geda-user] Hierarchical pcb design |
In-reply-to: | <87h71caekv.fsf@lepton.mail-host-address-is-not-set> |
References: | <20220910234819 DOT 6013F8071ECF AT turkos DOT aspodata DOT se> <87h71caekv DOT fsf AT lepton DOT mail-host-address-is-not-set> |
Comments: | In-reply-to "Vladimir Zhbanov (vzhbanov AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
message dated "Mon, 12 Sep 2022 16:30:11 +0300." | |
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Date: | Mon, 12 Sep 2022 17:09:09 +0200 (CEST) |
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Vladimir: ... > I'm interested. Good test designs would be a nice start for working on > this and are always welcome in Lepton. ... Good, I'm on! I'll put it in (nothing there yet): http://aspodata.se/electronic/hier_design/ Regards, /Karl Hammar
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