Mail Archives: geda-user/2022/09/10/20:08:43
At the schematic level designing with subsheets is established.
I want to make that possible at the pcb level also.
By comparing net-files for the whole design and the net-file
for a subsheet (as if it was the complete design), I realise
that what is need to make this happen is to prepend the refdes's
of the elements in the sub pcbs, rm their netlist() since the
net file for the complete design contains the nets for all sub
designs.
For example:
tot.sch contains a src symbol with refdes=s and source=sub.sch
Run lepton-sch2pcb/gsch2pcb as usual but on sub.sch,
make a sub.pcb which realises the design in sub.sch.
Prepare the sub.pcb by running ([1])
pcb_shrink.pl refdes the.pcb > new_file.pcb, e.g.
pcb_shrink.pl s sub.pcb > ssub.pcb
Now run sch2pcb on tot.sch
Open tot.pcb with pcb, load layout -> ssub.pcb and place it somewhere
load layout -> tot.new.pcb, load net file etc.
Seems to work fine, except the when I load the ssub.pcb it is upside
down in the buffer.
///
pcb_shrink.pl removes symbol[] and netlist() from the orig file,
and adds the given refdes as a prefix on all elements in sub.pcb.
This code is just a prototype for a proof of concept, it isn't
final in any way.
I'd like this functionality to be included in resp. upstream
repo. If anyone is interested I'll make a example design for
this.
What is missing is the ability to cut/copy to buffer and move
the whole buffer to the other side of the board. Do anyone
know if that already is implemented ?
Regards,
/Karl Hammar
[1] http://aspodata.se/git/openhw/bin/pcb_shrink.pl
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