delorie.com/archives/browse.cgi   search  
Mail Archives: geda-user/2020/10/25/11:38:35

X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f
X-Recipient: geda-user AT delorie DOT com
X-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=gmail.com; s=20161025;
h=mime-version:references:in-reply-to:from:date:message-id:subject:to;
bh=UiQhgFMZylqjQ6uCuXvEqS65NUwkWc5ZUaKw6ffjFbk=;
b=GlJ2GnQqgZ3pdHX7TfCsN8cEZyVekLmln2QyxF78Zp18VmoqqnBfT9czDAOhp9rdv4
NbFXR7AdzfpwaMmQpCuD89g4b3HHDbSLr71AsPhIvteZxu/DDPHcAePFDrM3ulEFBmTA
2MRzglaxchZrmI4KBeLmYEjWlTPoMWzZWM/8eAj9yOWNYLm0da6ADvZgA33vN2Kl9NS6
cSVzFbEgQTCa0uCdnfVXW121+QKMMtwlqMxuuJRAx5PoYdxuDPYZ1a8D8qaLZgmRyyuI
eHpH4ygd93/UgcFyaTqtYlzezmNWOoebvpGhBT6YvIgU4Ti1y7q9pdsOhEgsTyM415Ve
TNmA==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20161025;
h=x-gm-message-state:mime-version:references:in-reply-to:from:date
:message-id:subject:to;
bh=UiQhgFMZylqjQ6uCuXvEqS65NUwkWc5ZUaKw6ffjFbk=;
b=NsdRQzO2nZ3o3D6vOreHEuVK0djVC79kSoMnapcSjnaiQ4nPkH0h8Q8kvXtljfikjd
LDCACSIOs87xI5nhHQgMFt/N5lpMcEVbXw1KHVSzzXhkS687ncBl2ie8psWGu0iYWR2+
ZNR+nWVoGxD05q7zF6u5wqi35SYhYH1rTrDo0CG74XXEIo3AJLlExLiYcAK8OIpaME+P
iwz60O7KRx+FhKinSEUmOPxLQ55RLaCbKKE4r+SvweToFG/wTJCg+1eeexrTsjCYe4/F
CgHLjc1djaNWGBF5ekMyRa8lpz3cTy31+fFr5qNnhspnzjOKKih/rniIWgQry8OMLGW4
lpDQ==
X-Gm-Message-State: AOAM531kCBgHNAvHod2+eGyXG5m+7vd3x8+ItUpsx6/UVcoJd/GKPcK+
i6UyvVEpKk+rl+gOONJTuM5pYXf2xTRCsymyZs/4rIq7TXs=
X-Google-Smtp-Source: ABdhPJwdclVwP2h3G6OkxGGAFJSYqTE934YyetAoVMQv2CX35PVeCZCcm7Fc+dS/hm1UOQRnpFII4nqT+G3s8wWemWI=
X-Received: by 2002:ab0:66d6:: with SMTP id d22mr12765271uaq.77.1603639107271;
Sun, 25 Oct 2020 08:18:27 -0700 (PDT)
MIME-Version: 1.0
References: <CAGBFkM1vXVKman8TP0eVE2=T8bPA-ao50xQ+VfFVuyTMaeh9RA AT mail DOT gmail DOT com>
In-Reply-To: <CAGBFkM1vXVKman8TP0eVE2=T8bPA-ao50xQ+VfFVuyTMaeh9RA@mail.gmail.com>
From: "Chad Parker (parker DOT charles AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Date: Sun, 25 Oct 2020 11:26:09 -0400
Message-ID: <CAJZxidDtJEAAjoGDLSncu4X7pnOWOWJhZpdJKE2kR+HKqbnhAg@mail.gmail.com>
Subject: Re: [geda-user] PCB, 2 parts physically in the same place
To: geda-user AT delorie DOT com
Reply-To: geda-user AT delorie DOT com

--000000000000563d8e05b2805301
Content-Type: text/plain; charset="UTF-8"

Hi Gene-

pcb will "allow" you to do basically anything. It should not prevent you
from overlapping the components. This shouldn't even generate a DRC warning.

As a general rule, pcb assumes that the human designer knows best and
shouldn't prevent you from doing most things. It may complain with a DRC
warning, but it won't actually prevent you from doing it.

Regarding the plane connection, pcb thermals should work for through-hole
components. The surface-mount thermals are implemented yet.

I assume that the overlap warning isn't the one at 0,0 that we discussed
previously? It's helpful to have the problematic file to evaluate. I've
just done a couple of quick tests, and I am able to do what you're
describing in my test cases.

Thanks,
--Chad

On Sat, Oct 24, 2020 at 9:41 PM gene glick (geneglick AT optonline DOT net) [via
geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:

> I want to do this on purpose. One part, a 2X16 character display has 10
> connections to the PCB. Problem is, they are just holes. It is meant to
> have a 10 pin header on the PCB, and then the display gets positioned over
> the header and soldered in place. So I placed a 10-pin header in the same
> location that the display holes. They line up perfectly but the sizes are
> slightly different (a little more or less annulus for example).
>
> I could simply get rid of the 10-pin header (yeah, I think that's the way
> to go in the short term), and remember to order it. If it's in the
> schematic though, it gets into the BOM...which is good.
>
> Anyway, PCB doesn't allow a couple of things - I cannot make a thermal
> connection to the plane on either top or bottom of board. Instead, I made
> some traces to the plane. Now DRC reports a problem with too little overlap.
>
> Is this a bug?
>

--000000000000563d8e05b2805301
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr"><div>Hi Gene-</div><div><br></div><div>pcb will &quot;allo=
w&quot; you to do basically anything. It should not prevent you from overla=
pping the components. This shouldn&#39;t even generate a DRC warning.</div>=
<div><br></div><div>As a general rule, pcb assumes that the human designer =
knows best and shouldn&#39;t prevent you from doing most things. It may com=
plain with a DRC warning, but it won&#39;t actually prevent you from doing =
it.<br></div><div><br></div><div>Regarding the plane connection, pcb therma=
ls should work for through-hole components. The surface-mount thermals are =
implemented yet.</div><div><br></div><div>I assume that the overlap warning=
 isn&#39;t the one at 0,0 that we discussed previously? It&#39;s helpful to=
 have the problematic file to evaluate. I&#39;ve just done a couple of quic=
k tests, and I am able to do what you&#39;re describing in my test cases. <=
br></div><div><br></div><div>Thanks,</div><div>--Chad<br></div></div><br><d=
iv class=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmail_attr">On Sat, Oct =
24, 2020 at 9:41 PM gene glick (<a href=3D"mailto:geneglick AT optonline DOT net">=
geneglick AT optonline DOT net</a>) [via <a href=3D"mailto:geda-user AT delorie DOT com">=
geda-user AT delorie DOT com</a>] &lt;<a href=3D"mailto:geda-user AT delorie DOT com">ged=
a-user AT delorie DOT com</a>&gt; wrote:<br></div><blockquote class=3D"gmail_quote=
" style=3D"margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);=
padding-left:1ex"><div dir=3D"ltr"><div>I want to do this on purpose. One p=
art, a 2X16 character display has 10 connections to the PCB. Problem is, th=
ey are just holes. It is meant to have a 10 pin header on the PCB, and then=
 the display gets positioned over the header and soldered in place. So I pl=
aced a 10-pin header in the same location that the display holes. They line=
 up perfectly but the sizes are slightly different (a little more or less a=
nnulus for example).</div><div><br></div><div>I could simply get rid of the=
 10-pin header (yeah, I think that&#39;s the way to go in the short term), =
and remember to order it. If it&#39;s in the schematic though, it gets into=
 the BOM...which is good.</div><div><br></div><div>Anyway, PCB doesn&#39;t =
allow a couple of things - I cannot make a thermal connection to the plane =
on either top or bottom of board. Instead, I made some traces to the plane.=
 Now DRC reports a problem with too little overlap.</div><div><br></div><di=
v>Is this a bug?=C2=A0<br></div></div>
</blockquote></div>

--000000000000563d8e05b2805301--

- Raw text -


  webmaster     delorie software   privacy  
  Copyright © 2019   by DJ Delorie     Updated Jul 2019