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Subject:	Re: [geda-user] A proposal to allow simulation only component to be
	embedded in schematics
To:	geda-user AT delorie DOT com
References:	<8e4ea0e5-a35f-59e3-8052-8e5901225461 AT epilitimus DOT com>
	<19E1ADF6-6DB0-44F2-B1BA-4FB0F34CF7E8 AT noqsi DOT com>
	<60f1ec51-d94b-e981-765b-a63b4012563c AT epilitimus DOT com>
	<BC5F3FDB-BB0E-4FEE-A784-2F1AA419257B AT noqsi DOT com>
From:	"Nicklas SB Karlsson (nk AT nksb DOT online) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Message-ID:	<9c3c750e-9c50-c12f-8660-ca9ca57b2a55@nksb.online>
Date:	Fri, 16 Oct 2020 23:43:47 +0200
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I will look at spice-noqsi further but seems like we are coming at the
>> problem from opposite directions. I am saying put the SOCs in the
>> schematic and remove them when doing non simulation output. The only way
>> I can see to do this without all the backends having to contain the same
>> SOC removal logic is to put it in gnetlist. To my way of thinking this
>> also allows for clean printout.
>>
>> Having separate test-fixture and layout versions puts you back into the
>> parallel design issue.
>
> Not really. The test fixture is a separate page that contains only 
> test components. There’s no parallel development for the pages that 
> represent the circuit you’re going to lay out.

Use hierarchical design there one top level is used in ordinary 
schematic while the other top level is used for simulation? Sometimes do 
it in a similar fashion with software where some kind of "test bench" in 
a sub folder

Nicklas Karlsson

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