Mail Archives: geda-user/2018/12/15/08:44:58
Hello Stephen,
On Sat, 15 Dec 2018, Stephen Ecob wrote:
>Hi Igor,
>
>I have used this feature to great advantage with FPGA based designs.
>I modified find.c to output the data in PCB netlist format. I then
>used a reverse flow where most of the physical layout is done first
>and leads to the netlist. This is an advantage with FPGAs as they
>have a very high degree of pin swapability and layout quality can be
>greatly improved by keeping the FPGA pinout minimally constrained
>(instead of completely constrained as occurs with a traditional flow).
Thanks!
Since those times, we have introduced back annotation - supported by the
git version of gschem and soon will be supported by xschem too. It's
exactly what you described: you can modify the netlist in PCB and then
send it back to the schematics capture softare that helps the user to
update the schematics to match what you have on the board (you may call it
"as built" version). Then on a new import pcb-rnd figures if the sch got
updated and removes the locally administrated deviations.
Would that make a good alternative to this custom export format?
>I don't have any FPGA PCB work scheduled at this time, but next time I
>do I will use this flow again. I'll either dust off my 2010 era
>modified PCB or port my code to pcb-rnd if I have time.
Cool, thanks! Let me know when this happens - I will give you svn write
access so the new format can be part of the official pcb-rnd distro - in
case the normal back annotation is not good for some reason.
Meanwhile I've finished the rewrite, managed to cut out the old find.c
code and moved the connection export code to a plugin (and the old DRC
code to another plugin). Will fully remove the old find.c code tomorrow -
finally! (This was one of the dark corners in the code base.)
The conn export plugin is really small, 224 sloc, so it'd be easy to add a
clone that does a different format.
Regards,
Igor2
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