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Mail Archives: geda-user/2018/07/15/04:45:10

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Date: Sun, 15 Jul 2018 10:50:26 +0200 (CEST)
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To: "Luis de Arquer (ldearquer AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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From: gedau AT igor2 DOT repo DOT hu
Subject: Re: [geda-user] Re: DRC clearance bugs [PATCH 1/2]
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On Sun, 15 Jul 2018, Luis de Arquer (ldearquer AT gmail DOT com) [via geda-user AT delorie DOT com] wrote:
>
> It can be applied to current master

Unfortunately these don't apply on pcb-rnd sources (obviously).

Besides the dual-bbox thing I wrote earlier, I like your patch, you are 
welcome to do similar in pcb-rnd. Our data model differs, has less 
restrictions, so I believe more cases need to be handled:

- line vs poly (present in mainline too)

- arc vs poly (present in mainline too)

- padstack vs poly (in mainline this is via vs. poly, pin vs. poly and pad 
vs. poly)

- poly vs poly (because pcb-rnd supports poly-poly clearances as well, so 
you can easily desing those cool PSU boards with real thick copper 
everywhere)

Regards,

Igor2


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