Mail Archives: geda-user/2018/07/10/22:28:49
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On Tue, 10 Jul 2018, Marvin Dickens (mpdickens AT gmail DOT com) [via geda-user AT de=
lorie.com] wrote:
>Well, I am not a unicorn...
>
>This bug has been around for over a *decade* and has been one of the deal
>breakers for us.
>A solid net list is required when bringing up non-trivial boards for the
>first time and later during DUT
>after engineering changes / repair.=C2=A0
Well, maybe time to switch to pcb-rnd then. We fixed most of these decade=
=20
old design errors, bugs, misfeatures already. Not by kludging some quick=20
hack on top of the existing bag-of-special-cases, but by switching to a=20
more orthogonal data model that avoids special casing.
Note: pcb-rnd is compatible. It can read and write the file format of=20
geda/PCB (just as it can read kicad, eagle, protel, etc. See:=20
http://repo.hu/projects/pcb-rnd/user/09_appendix/bridges.svg )
About your specific case:
In pcb-rnd, for a year already, you can have copper in footprints that are=
=20
not "pins" or "pads", thus are invisible to netlist. Still you can make=20
them look exactly like pins or pads (remove solder mask above them or add=
=20
paste, add thermal, etc).
More technically speaking, the features you may be interested in:
- We don't have the old pcb element limitations, such as only pins/pads=20
can create copper or mask or paste objects in elements; you can have any=20
object in a footprint, on any layer.
- the mask and paste layers are not special hacks anymore that can be
accessed through smd pads and pins and vias only; they are explicit
layers, exactly like any copper layer, and you can draw on them. (This is=
=20
like that for about 1.5 years already.)
- We have a "new" (~8 months old) pin/pad/via replacement, padstack; we=20
have fully decoupled the "part of the netlist" thing from the geometry, so=
=20
you can basically go there to any padstack and just remove the terminal id=
=20
("pin number") and while there is zero change in the geometry, it=20
immediately becomes invisible to the netlist. (In return you don't have to=
=20
use the padstack object to make a netlisted thing; just assign a temrinal=
=20
ID to any copper object and boom, it's a pad)
- Bonus: a padstack can have any shape and you can have thermals on it.=20
Yes, this does mean proper, on-click thermal on SMD pads. See:=20
http://repo.hu/cgi-bin/pool.cgi?cmd=3Dshow&node=3Dthermals
- Bonus 2: we have some extra minor features related to these things, for=
=20
years already: the "nonetlist" flag that cna make an entire footprint=20
invisible to the netlist (so you can place your mounting holes or test=20
pads or 0 ohm SMD jumpers without having to add them to the schematics);=20
the "intconn" for terminals, so you can tell pcb-rnd that your=20
footprint's pin/pad 2 and 15 are galvanically connected internally in the=
=20
package.
- Bonus 3: padstacks can have any shape, not just round or square or=20
octagon. This includes oblong/oval shape or arbitrary polygon shape. You=20
can have different shape/size on internal copper layers or top or bottom=20
copper layer or basically on any layer as there's no more magic=20
(automatically generated side effect shapes, like mask and paste was in=20
PCB)
Regards,
Igor2
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