Mail Archives: geda-user/2018/05/15/09:24:12
--2DKRVTMQSMTFXVUJYGXQRnhgwp
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset=UTF-8
Hello Igor, Have You received any mail from me recently? I'm not sure=
what about the missing test You mentioned last time. Best Regards, Micha=
el Widlok
Dnia 11 maja 2018 09:35 michalwd1979 <gedau AT igor2 DOT repo=
.hu> napisa=C5=82(a):
Hello Michael,
On Tue, 8 May 2018, michalwd1979 (michalwd1979 AT o2 DOT pl) [via geda-user AT delor=
ie.com] wrote:
RU200 is really the un-even Wilkinson splitter. The layout of it was given=
to me in a dxf format, so I had to create a scaled background image and=C2=
=A0
then draw polygons on it. Then the polygons were converted to a footprint =
or
Btw, we have a hpgl import plugin. Most CADs that can save in dxf can also=
plot in hpgl. We don't yet deal with polygons, but it'd be easy to=
add and
then no redraw needed for such cases.
<snip>
As for vias that was a bit boring but not to much... The vias are the last=
thing placed on the pcb so I had a nice felling of work-ending-soon when
placing them :-).
I thing that via-lines would be really useful only if the vias would be
configurable in some way: connect using thermal X to polygon Y, with
clearance Z or something. For example You create a via with all the
specification needed and then "extend" it to a via-line. Was that =
Yours
idea? If yes then I would really like it.
Yes. In pcb-rnd terminology your via is really a padstack, and a padstack =
has a prototype (that describes the geometry). So for a via-line, you'=
d
select a padstack prototype and all vias on that line would be using that.=
Just like multiple vias can share the same prototype today, multiple
via-lines could share the same prototype. This means if you change the
geomerty of the prototype, that immediately affects all instances.
Another extra parameter for the via-line would be the spacing between vias=
and how to enforce it (e.g. make sure endpoints have vias and tune the
spacing to meet that, or rather keep the spacing as specified and don'=
t
mind if the second endpoint won't have a via).
I also plan to have via-polygons - same story as via-lines: an evenly
spaced grid of vias over an area specified by a virtual polygon. Would be =
useful for those via grids under center pads of QFNs.
Btw, any news on the dash-freq test on your system? We really need to know=
the result to be able to go on with narrowing down what's causes the
rendering slowness there.
Regards,
Igor2=0D
--2DKRVTMQSMTFXVUJYGXQRnhgwp
Content-Transfer-Encoding: quoted-printable
Content-Type: text/html; charset=UTF-8
<div>Hello Igor,<br></div><div><br></div><div>Have You receiv=
ed any mail from me recently? I'm not sure what about the missing test You =
mentioned last time.<br></div><div>Best Regards,<br></div><div>Michael Widl=
ok<br></div>
<br>
<div class=3D"nh_extra">
<p>
Dnia 11 maja 2018 09:35 michalwd1979 <gedau AT igor2 DOT repo=
.hu> napisa=C5=82(a):
</p>
<blockquote class=3D"nh_quote" style=3D"border-left: 2px so=
lid #999; padding-left: 8px; margin: 0;">
<div id=3D"gwp3cc5df9c"><div>Hello Michael,</div>
<div><br></div>
<div>On Tue, 8 May 2018, michalwd1979 (michalwd1979 AT o2 DOT pl) [via geda-user AT d=
elorie.com] wrote:</div>
<div><br></div>
<blockquote is-minimized>
<div>RU200 is really the un-even Wilkinson splitter. The layout of it was g=
iven</div>
<div>to me in a dxf format, so I had to create a scaled background image an=
d=C2=A0</div>
<div>then draw polygons on it. Then the polygons were converted to a footpr=
int or</div>
</blockquote>
<div><br></div>
<div>Btw, we have a hpgl import plugin. Most CADs that can save in dxf can =
also </div>
<div>plot in hpgl. We don't yet deal with polygons, but it'd be eas=
y to add and </div>
<div>then no redraw needed for such cases.</div>
<div><br></div>
<div><snip></div>
<div><br></div>
<blockquote is-minimized>
<div>As for vias that was a bit boring but not to much... The vias are the =
last</div>
<div>thing placed on the pcb so I had a nice felling of work-ending-soon wh=
en</div>
<div>placing them :-).</div>
<div>I thing that via-lines would be really useful only if the vias would b=
e</div>
<div>configurable in some way: connect using thermal X to polygon Y, with</=
div>
<div>clearance Z or something. For example You create a via with all the</d=
iv>
<div>specification needed and then "extend" it to a via-line. Was t=
hat Yours</div>
<div>idea? If yes then I would really like it.</div>
</blockquote>
<div><br></div>
<div>Yes. In pcb-rnd terminology your via is really a padstack, and a padst=
ack </div>
<div>has a prototype (that describes the geometry). So for a via-line, you&=
#39;d </div>
<div>select a padstack prototype and all vias on that line would be using t=
hat.</div>
<div><br></div>
<div>Just like multiple vias can share the same prototype today, multiple <=
/div>
<div>via-lines could share the same prototype. This means if you change the=
</div>
<div>geomerty of the prototype, that immediately affects all instances.</di=
v>
<div><br></div>
<div>Another extra parameter for the via-line would be the spacing between =
vias </div>
<div>and how to enforce it (e.g. make sure endpoints have vias and tune the=
</div>
<div>spacing to meet that, or rather keep the spacing as specified and don&=
#39;t </div>
<div>mind if the second endpoint won't have a via).</div>
<div><br></div>
<div>I also plan to have via-polygons - same story as via-lines: an evenly =
</div>
<div>spaced grid of vias over an area specified by a virtual polygon. Would=
be </div>
<div>useful for those via grids under center pads of QFNs.</div>
<div><br></div>
<div><br></div>
<div><br></div>
<div>Btw, any news on the dash-freq test on your system? We really need to =
know </div>
<div>the result to be able to go on with narrowing down what's causes t=
he </div>
<div>rendering slowness there.</div>
<div><br></div>
<div>Regards,</div>
<div><br></div>
<div>Igor2</div>
</div>
</blockquote>
</div>
--2DKRVTMQSMTFXVUJYGXQRnhgwp--
- Raw text -