Mail Archives: geda-user/2018/05/07/09:03:20
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Igor, I made a few more tests: My board but with removed vias and remove=
d polygons: It is faster but still very slow: benchmark says 0.8, my percep=
tion is much less then that - waiting about 3s for a board move (panning).=
=C2=A0 My board without 2 "middle" layers, no vias, no polygons: =
as before, however - I noticed massive speedup when "subcircuits"=
layer is off. With complete board benchmark is 8.3, full screen window (si=
ngle 1600x1200). This is still slower then opengl pcb (with all layers ON) =
but we are getting closer. Best Regards, Michael Widlok Dnia 7 maja 201=
8 11:36 michalwd1979 < gedau AT igor2 DOT repo DOT hu > napisa=C5=82(a): Hello=
Michael, On Mon, 7 May 2018, michalwd1979 ( michalwd1979 AT o2 DOT pl ) [via =
geda-user AT delorie DOT com ] wrote: Hello pcb-rnd Developers, Igor, results=
for Yours tests (with the straight lines and my board) are in attached fi=
le. For the straight lines and GL, it seems that the performance is=C2=A0 =
similar to Yours, window on both screens (3200x1200) gives 19FPS. With my =
board (test.pcb, also attached) benchmark seems to suck at 0.4FPS, because=
my felling is that it is even slower. I don't have lesstif and pcb-rn=
d was compiled with -O2, no debugging. Thank you! The next thing to tr=
y is the multi-layer version, to see if it is the layer compisiting that g=
ets slower in our version. I will be able to produce that test file tomorr=
ow morning. If the answer will be yes, I have ideas how we could optimize=
it. If the answer will be no, I will take your board apart to see what ki=
nd of (or combination of) object(s) cause the problem. Adrian, pleas fi=
nd the board attached. This is a RF board, so it is bloated with vias and =
polygons. It was created with my local patched opengl pcb version, with 8 =
routing styles and solid thermals on pads. FYI, with pcb-rnd you don'=
t need a patch (or any compile time configuration) for 8 routing styles - =
we support a virtually unlimited number of routing styles. Best regards,=
Igor2=0D
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Igor,<br><br>I made a few more tests:<br>My board but with removed vias and=
removed polygons: It is faster but still very slow: benchmark says 0.8, my=
perception is much less then that - waiting about 3s for a board move (pan=
ning). <br><br>My board without 2 "middle" layers, no vias, no polygon=
s: as before, however -<br><br>I noticed massive speedup when "subcircuits"=
layer is off. With complete board benchmark is 8.3, full screen window (si=
ngle 1600x1200). This is still slower then opengl pcb (with all layers ON) =
but we are getting closer.<br>Best Regards,<br>Michael Widlok<br><div><br><=
/div><div class=3D"nh_extra"><p>Dnia 7 maja 2018 11:36 michalwd1979 <<a =
href=3D"mailto:gedau AT igor2 DOT repo DOT hu">gedau AT igor2 DOT repo DOT hu</a>> napisa=C5=
=82(a):<br></p><blockquote class=3D"nh_quote" style=3D"border-left: 2px sol=
id #999; padding-left: 8px; margin: 0;"><div id=3D"gwp8d79d9c2"><div>Hello =
Michael,<br></div><div><br></div><div>On Mon, 7 May 2018, michalwd1979 (<a =
href=3D"mailto:michalwd1979 AT o2 DOT pl">michalwd1979 AT o2 DOT pl</a>) [via <a href=3D"=
mailto:geda-user AT delorie DOT com">geda-user AT delorie DOT com</a>] wrote:<br></div><d=
iv><br></div><blockquote is-minimized=3D""><div>Hello pcb-rnd Developers,<b=
r></div><div><br></div><div>Igor, results for Yours tests (with the straigh=
t lines and my board) are in<br></div><div>attached file. For the straight =
lines and GL, it seems that the performance<br></div><div>is similar =
to Yours, window on both screens (3200x1200) gives 19FPS. With<br></div><di=
v>my board (test.pcb, also attached) benchmark seems to suck at 0.4FPS,<br>=
</div><div>because my felling is that it is even slower. I don't have lesst=
if and<br></div><div>pcb-rnd was compiled with -O2, no debugging.<br></div>=
</blockquote><div><br></div><div><br></div><div>Thank you!<br></div><div><b=
r></div><div>The next thing to try is the multi-layer version, to see if it=
is the<br></div><div>layer compisiting that gets slower in our version. I =
will be able to<br></div><div>produce that test file tomorrow morning.<br><=
/div><div><br></div><div>If the answer will be yes, I have ideas how we cou=
ld optimize it. If the<br></div><div>answer will be no, I will take your bo=
ard apart to see what kind of (or<br></div><div>combination of) object(s) c=
ause the problem.<br></div><div><br></div><div><br></div><blockquote is-min=
imized=3D""><div>Adrian, pleas find the board attached. This is a RF board,=
so it is bloated<br></div><div>with vias and polygons. It was created with=
my local patched opengl pcb<br></div><div>version, with 8 routing styles a=
nd solid thermals on pads.<br></div></blockquote><div><br></div><div>FYI, w=
ith pcb-rnd you don't need a patch (or any compile time<br></div><div>confi=
guration) for 8 routing styles - we support a virtually unlimited<br></div>=
<div>number of routing styles.<br></div><div><br></div><div>Best regards,<b=
r></div><div><br></div><div>Igor2<br></div></div></blockquote></div><div><b=
r></div>
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