Mail Archives: geda-user/2018/02/09/20:59:21
On 02/09/2018 05:30 PM, Anton Dubniak (twister AT tfsoft DOT org DOT ua) [via geda-user AT delorie DOT com] wrote:
> They should not be tented, as the trapped air will prevent the tension forces to do its job and solder will not be sucked inside
> the vias, which, in turn, will not result in a good thermal contact.
What about the problem of voids in solder contact to the central pad. I find cases written up and some manufacturer
recommendations to take steps to stop wicking of solder into vias.
My case is OK without much heat transfer and will have good heat transfer because of manual prototyping methods,
but want to get it right before going to production boards.
cypress.com "There is no thermal relief (web or spoke connections) on vias. Do not completely cover vias with solder mask
because it can lead to excessive voiding. To avoid wicking, vias should be internally plated with copper and filled with solder."
lattice.com "The optimum and reliable solder joints on the perimeter pads have about 50 to 70 um (2 to 3 mils) standoff height.
Tightly control the stencil aperture tolerance because these tolerances can effectively reduce the aperture size.
Area ratios of 0.66 and aspect ratios of 1.5 were never exceeded. The land pattern on the PCB should be 1:1 to the
land pads on QFN package.
Stencil thickness of 0.125 mm is recommended for 0.5 mm dual-row QFN packages. A laser-cut stainless steel
stencil with electro-polished trapezoidal walls is recommended to improve the paste release. Lattice recommends
that no-clean, Type 3 or Type 4 paste be used for mounting QFN packages. Nitrogen purge is also recommended
during reflow."
nxp/freescale combined document:
"Maximum thermal and electrical performance is achieved when an array of vias is
incorporated in the land pattern at a 1.20 mm grid, as shown in Figure 21
.
•
It is recommended that the via diameter be 0.30 to 0.33 mm with 35 μm Cu plating
thickness (1.0 oz/ft
2
). This is desirable to avoid any solder-wicking inside the via
during the soldering process, which may result in solder voids in the joint between the
exposed pad and the thermal land.
•
If the copper plating does not plug the vias, then the thermal vias can be “tented” with
solder mask on the top surface of the PCB to avoid solder wicking inside the via during
assembly. The solder mask diameter should be at least 0.10 mm larger than the via
diameter."
"No-clean flux doesn’t require cleaning, but normally a little residue remains on the
PCB after soldering. In general, it is recommended to use a no-clean solder paste,
because cleaning of flux residues from underneath the package is not feasible for a
QFN/SON-style package (due to the low package standoff)."
[jg]It's technically difficult. 0.33mm is smaller than cheap fabs minimum drill size...
I just got some boards back from a hobbyist oriented fab, jlcpcb.com where they dropped my paste layer
and auto-generated their own...and they upped drill sizes.
The nxp/freescale recommendation to use mask on the top layer is something I had not thought of, (rejected before thinking about
it), and it seems aligned with making sure the QFN is floating on at least 60 microns of hot solder. And it gets away from the
air pocket of tented on the bottom side vias. Using that and as close spaced vias as your fab allows is a no extra
steps method of getting good heat transfer and still floating the QFN on the hot solder instead of wicking pulling it dry
and having voids.
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