Mail Archives: geda-user/2017/11/04/09:06:24
(... padstack announcement continued)
If you are interested in "thermal on smd pad", read on. Pcb-rnd can
already do that with padstacks.
A padstack normally includes shapes, one per layer type. "Normally",
because it's optional: for example the simplest mounting hole can be a
padstack that has an unplated hole and no shapes at all. The hole is
optional too: an smd pad typically contains shapes (e.g. for top copper,
top mask and top past but no hole.
A shape is a filled circle, a line (round or square cap) or an arbitrary
shaped convex polygon. The shape doesn't have to be centered at the hole.
Restrictions: only one shape per layer type, only one hole per padstack.
(This is enough for vast majority of the use cases, for the rest, heavy
terminals in subcircuits shall be used; a heavy terminal can contain
anything that can be drawn on a PCB, without restriction.)
Since an arbitrary shaped pin or via needs to be able to make a thermal,
the thermal code got upgraded to handle all the above shapes. A matrix of
how they each look can be found at:
http://repo.hu/projects/pcb-rnd/devlog/20171104/thermals.png
among with the source board if you want to play with the padstacks:
http://repo.hu/projects/pcb-rnd/devlog/20171104/thermals.lht
And yes, this _does_ mean smd pads can have thermals, as long as they are
done with the new padstacks, and not the old pad objects.
The ability to have different shape per layer type makes it easier to use
the inner layers of dense boards: outer layers can have larger pads for
better soldering of through-hole pins, while inner pads can be as small as
the fab permits, to allow more traces to pass between them.
A padstack instance can be rotated and mirrored, still referring to the
same central padstack prototype for the shapes. A padstack instance can
have a different clearance, still using the same prototype. If a padstack
instance needs to deviate, it's very cheap to copy the prototype and
starts its own group with the deviations included.
There are two features I have not decided about yet, but will do in a few
days:
- I have half-working code for a "thermal style" that removes the copper
shape on a specific layer group; this again could be used for saving space
on inner layers
- I have half-working code for a per-shape clearance; it may be that I
will provide both a global, per pad stack instance clearance option and a
padstack prototype defined per shape clearance. Rationale: some IPC
suggests the clearance on inner layers can be tighter than on outer
layers, for various reasons. This may matter on dense boards.
If you have constructive thoughts about these features, please share.
Regards,
Igor2
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