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	Thu, 20 Jul 2017 11:42:07 -0700 (PDT)
Date:	Thu, 20 Jul 2017 20:42:06 +0200
From:	"Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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> > xschem:
> > VHDL / Verilog / Spice netlist, ready for simulation
> > Behavioral VHDL / Verilog code can be embedded as one of the properties of the schematic block
> > 
> > 
> > These xschem abilities will be good goals to include in cschem.
> 
> 
> We already have these for SPICE in gEDA and Lepton if you use the gnet-spice-noqsi back end (https://github.com/noqsi/gnet-spice-noqsi <https://github.com/noqsi/gnet-spice-noqsi>) for gnetlist. I believe both Lepton and Roland’s gnetlist replacement now give the back end writer enough support to do Verilog and VHDL right. So, we don’t need a new tool, just a couple of new back ends.

Yes, I never had any problem to express any circuit in gschem. There are a few things missing but not many.

Then it come to available libraries and backends the story is a little bit different. Predefined attributes should ideally be part of the backend. Online design rule check would be possible if backend is a plugin. I heard something about documentation layer in pcb-rnd useful to feedback data generated externally.

> 
> John Doty              Noqsi Aerospace, Ltd.
> http://www.noqsi.com/
> jpd AT noqsi DOT com

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