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xschem:
VHDL / Verilog / Spice netlist, ready for simulation
Behavioral VHDL / Verilog code can be embedded as one of the properties of the schematic block


These xschem abilities will be good goals to include in cschem.

When the netlist output is verilog and the included blocks embed their verilog in the netlist,
the resulting verilog netlist is complete for the system.  So that is good for chip design,
or printable electronics system design, where you want to test against the complete system
in whatever way you can before spending money on a chip fab run or a print run.

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