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	Thu, 06 Jul 2017 08:14:20 -0700 (PDT)
Date:	Thu, 6 Jul 2017 17:14:16 +0200
From:	"Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] Refdes= mangling
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> Hi, fellow gEDA users,
> 
> ...
> 
> Now, one of my ideas is to move mangling of hierarchy related
> attributes to the post-processing stage in order to process schematic
> pages and subpages separately, creating isolated subcircuits first.

Sounds reasonable, only problem with name hierarchical name is they get to long to fit on circuit board.

> After some time of thinking, I realise the use cases when net= is
> mangled or not. The former case is for subcircuits that share their
> power sources, the latter is for such cases where such power sources
> are would-be-isolated within the subschematics.

If alias is possible I think it is a good idea to use for old or new name?

> Are there use cases where it is OK to use refdes= without mangling in
> flattened hierarchical schematic netlist? I see only a field for
> various potential conflicts...
> 
> Thank you,
>   Vladimir
> 
> [1] https://github.com/lepton-eda/lepton-eda/pull/139


Not related but I think there is a problem with lowercase letters in gnetlist and maybe space for net names then, at least then using them in pcb they do now show up in list of known nets.

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