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From:	"miloh (miloh AT froggytoad DOT net) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Date:	Tue, 4 Jul 2017 10:18:39 -0700
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Subject:	Re: [geda-user] Raspberry Pi "hat"
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On Tue, Jul 4, 2017 at 5:21 AM, Sabin Iacob (iacobs AT m0n5t3r DOT info) [via
geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:
> On 07/03/2017 11:04 PM, Britton Kerin (britton DOT kerin AT gmail DOT com) [via
> geda-user AT delorie DOT com] wrote:
>> On Mon, Jul 3, 2017 at 11:26 AM, Dave McGuire (mcguire AT neurotica DOT com)
>> [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:
>>>   Would anyone happen to have a PCB outline/template/etc for a Raspberry
>>> Pi 2 "hat" board, the 40-pin connector version?
>> Not at the moment but by chance I was about to make one.  I can do
>> this pretty easily
>> as I already have one for the beaglebone black that can just be
>> tweaked.
>
>
> do you by any chance have that one somewhere online? maybe also the
> symbol... I need to make a breakout board for a BBB and the thought of
> drawing a beelion holes is ... less than exciting :)
>
>

I made some BBB revC parts for gEDA  a few years back, they worked but
there were a few problems to hack around:

https://raw.githubusercontent.com/miloh/gpcb-footprints/master/beagleboneblack.fp
https://raw.githubusercontent.com/miloh/gpcb-footprints/master/beaglebone-pins.fp

When I used these files, I placed the first 'beagleboneblack.fp' as a
template for a (hat?) design that would be pluggable to the BBB (revC
I believe). The pins included are registration references to mounts or
to the pin 1 location of the P8/P9 headers.

The pin footprint above doesn't have the correct pinnames to fit with
the symbols (linked below). So after placing the above two footprints
for registration references and outline information, the designer must
cleanup the footprint/symbol matchup, or add another round of plain
header footprints (using 0.1" headers from the stock library) to make
it all work. The outlines need to be moved from silk to the
appropriate layer.

Now, I would redesign these using subc in pcb-rnd, taking care of a
set of the above issues.

Finally regarding schematics and symbols. For the symbols I went ahead
and used gpios to work with the above layouts. This is somewhat cruel
to a designer who doesn't have a roadmap of the AM335x in their brain:

https://raw.githubusercontent.com/miloh/geda-symbols/master/BBB_CAPEHEADER_P9.sym
https://raw.githubusercontent.com/miloh/geda-symbols/master/BBB_CAPEHEADER_P8.sym

I wonder if there is a way CAD can help in these cases? Roughly, I
want to have symbols with cycling potential netnames, in order to aide
in the creation of devicetree overlays, and to simplify/adjust layout.
It would be an interesting improvement for a schematic editor in an
age of crossbar switch IO uc's and fpgas, and I hope to find new or
existing floss schematic editors that handle this well.

-r. miloh

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