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	Fri, 17 Mar 2017 14:09:12 -0700 (PDT)
Date:	Fri, 17 Mar 2017 22:09:01 +0100
From:	"Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] [pcb-rnd] tEDAx footprint load support
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> Question (to all PCB engineers): how often do you rely on the clearance 
> value set in a footprint?

I would say clearance in footprint is of very little or no use at all.

For copper I only rely on clearance between nets, for most nets a standard value usually a little bit larger than board manufacturer minimum clearance. A minimum solder mask width which is actually minimum distance since this layer is negative is common for design rule check. Silkscreen have a limited resolution which may show up in a design rule as clearance between objects.

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