Mail Archives: geda-user/2017/02/16/13:09:22
Milan Prochac (milan AT prochac DOT sk) [via geda-user AT delorie DOT com] wrote:
> On 15.02.2017 20:45, Bert Timmerman (bert DOT timmerman AT xs4all DOT nl) [via
> geda-user AT delorie DOT com] wrote:
>> Hello list members,
>>
>> It has been almost a month to this day that a new release of pcb was
>> done.
>
> As I use version from git, I cannot answer these question. But it do
> not see big changes there.
>
> Now - when stable version is out - it is good time to think about the
> plans for next release and maybe about some more significant
> improvements.
>
> What about blind/buried vias?
>
> Milan
>
>>
>> In this month there have been some 709 downloads of the tarball.
>>
>> What we active developers would like to have feedback on is:
>>
>> 1) how many list members have downloaded the tarball ?
>>
>> (0 or +1 suffices)
>>
>> 2) how many list members have tried to build an run the new version
>> of pcb ?
>>
>> (0 or +1 suffices)
>>
>> 3) what was your user experience ? (what went good, what went bad,
>> what was the first impression after test driving, etc.).
>>
>> (you can put the whole rant here ;-)
>>
>>
>>
>> If you didn't download the tarball you can do that from:
>>
>> https://sourceforge.net/projects/pcb/files/pcb/pcb-4.0.0/
>>
>>
>> We hope to here from you soon ;-)
>>
>> Thanks in advance and with kind regards,
>>
>> Bert Timmerman
>>
>
>
Hi Milan,
Peter Clifton, Rob Spanton and I discussed your work at FOSDEM.
We looked into your commits and we were really impressed.
Basically this is a go and will go into master very soon (do a rebase,
see if it builds, merge to master and push ... might happen this weekend).
These commits might need a few tweaks and further testing to make sue
the DRC (and ERC) is 100% correct handling this feature.
What we need to do is to make the layer stack definition in the pcb a
formal order because after applying these commits the layer stack order
will do matter.
What this means is that "top" needs to be first entry in the list of
layer(groups) regardless of the name it has.
As it is in the current situation (4.0.0) we can move layer(groups)
up/down as we like, this will not change connectivity (unless outer
layer(groups) are moved to inner layers, you will lose connectivity with
SMT components).
When pushed I will notify this list as to get things tested in a broader
audience and get bugs exposed (if any).
I aim for a bug release 4.0.1 (or a feature release 4.1.0) at the end of
March (this year ;-), and all unsolved bugs at that time will be dealt
with in following bug/feature releases 4.0.2 (or 4.1.1) end of June.
I hope we can keep master in a stable condition and do 4 releases per
year ;-)
For more details on the current roadmap have a look at:
https://launchpad.net/pcb/+milestones
Please do not focus on version numbers, focus on expected release dates ;-)
Nothing is set in stone, so please give a shout when things need to go
in a different order (you might get a request to assist with the changes
you require though ;-).
I hope the above answers your questions.
Kind regards,
Bert Timmerman.
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