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Date: | Thu, 19 Jan 2017 05:47:11 +0100 (CET) |
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To: | "Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
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From: | gedau AT igor2 DOT repo DOT hu |
Subject: | Re: [geda-user] [pcb] why no clearpoly on silk |
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On Wed, 18 Jan 2017, Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com] wrote: > > >On 18 Jan 2017 11:11, "Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via >geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> wrote: > Maybe I got something wrong. Normally clearance is between > copper while the silk is painted on both? > > >You are correct, but there is no technical reason why you can't make lines >on silk cut into (clear against) polygons on silk. > >Doing this makes the code and behaviour more consistent, although there is >not the electrical reason for requiring it. I completly agree. >This said, you can't necessarily extend the logic completely to match. For >example, I toyed with connectivity based island removal - that wouldn't make >sense on silk layers. > >Thinking about it, whilst you could use the "keep biggest piece" rule with >silk, I'd be tempted to just start with "full polygons" only. (For the >default flags if importing an old board). You are right. So the full(?) set of rules with silk-poly vs. old files could be this: Import-old would remove clear poly and set full poly. This would prepare for the case when the user sets the clear poly flag later. Export-old would remove the full poly and add clear poly. Just to keep the looks of the old format, to get diff-free round trips. (Why I think it doesn't matter beyond the looks: old code would not cut into silk-polys and new code loading old files would overwrite the flags on load anyway.) Regards, Igor2
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