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Subject: | Re: [geda-user] QFN packages solder mask |
To: | geda-user AT delorie DOT com |
References: | <2df480cc-5ef2-9ac6-b7ad-d17788a6b8b9 AT ecosensory DOT com> |
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From: | "John Griessen (john AT ecosensory DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
Message-ID: | <9bbf8308-06e1-0d9b-85a7-0980e8525481@ecosensory.com> |
Date: | Wed, 18 Jan 2017 19:43:32 -0600 |
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On 01/18/2017 06:09 PM, John Luciani (jluciani AT gmail DOT com) [via geda-user AT delorie DOT com] wrote: > I am suggesting a single center copper pad on the PCB and multiple pads cut in the solder stencil. All of the QFN > application notes I have read recommend similar things. Checkout TI SLUA271A "QFN/SON Attachment" or > NXP SOT1189-1 footprint recommendation. There are a lot more notes out there but these are the two I found quickly. > The TI datasheets usually have detailed recommendations. I made that footprint with 9 center pads instead of one based on reading this from NXP/Freescale division: http://www.nxp.com/assets/documents/data/en/application-notes/AN1902.pdf > For devices with vias I add them to the footprint. For each device with a power pad I make a stencil footprint > with the same name but a sfp extension. When making the stencil you can have a script replace footprints > with stencil footprints. Ah so. That gets around the limitations of generated paste layer... Redefine everything with a make script for getting paste layer output. Good thinking -- not compromised -- can tweak and get high yield.
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