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From:	"Svenn Are Bjerkem (svenn DOT bjerkem AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Date:	Thu, 1 Sep 2016 23:22:43 +0200
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Subject:	Re: [geda-user] Can an attribute be attached to text for later
	inclusion in gnetlist backend?
To:	geda-user <geda-user AT delorie DOT com>
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On 1 September 2016 at 00:14, Vladimir Zhbanov (vzhbanov AT gmail DOT com)
[via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:
> Svenn,
>
> On Thu, Aug 25, 2016 at 08:11:26AM +0200, Svenn Are Bjerkem (svenn DOT bjerkem AT googlemail DOT com) [via geda-user AT delorie DOT com] wrote:

>
>> I have so many thoughts about how gschem/gnetlist can help me organize
>> "throwaway" testbenches for my vhdl design, but it is all a side
>> project to my daily work.
>> I am working on my own version of a vhdl back-end, but I am not very
>> far at the moment. Learning.
>
> OK, probably we could work together to make something useful
> then. I am going to publish my changes made so far somewhere, so
> if you're interested, we could discuss the topic.

I can discuss, but I am not good in scheme yet.


>>
>> I am also looking into choosing top-level attribute names which will
>> work the same accross vhdl, verilog and vams backends so that the
>> schematic can be used with little modification on different types of
>> simulators.
>
> There are too many different simulators. I believe we could
> concentrate on a limited subset, say, spice, verilog and/or vhdl.

I noted that the verilog back-end expects the attribute which define
the name of the module to build a netlist for to be module-name and
the vhdl back-end expects the attribute to be module_name. I don't
know what the spice back-end expects.

>
>>
>> My main target is to just create top-level block-type schematics. I am
>> not sure gnetlist could handle a "real" hierarchical design. I know
>> too little about its capabilities.
>>
>
> If I would know what is "real" hierarchical design... ;-) Yes,
> gnetlist has many limitations, though it has some means for
> working with hierarchical schematics.

I find it hard to describe what makes a design a real hierarchical
design other than that a symbol can represent a new schematic filled
with symbols which again represent schematics. Kind of the way scheme
works recursively into its problem solution. geda users make
hierarchical spice netlists all the time, so I am not sure what really
is the snag with gnetlist here, but for my most frequent use-case, a
schematic will be one level only where each symbol represent a file
with vhdl code (or verilog).

-- 
Svenn

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