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From:	"Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Date:	Sat, 27 Aug 2016 02:04:57 +0000
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Subject:	Re: [geda-user] Microwave PCB layout simulation or How to eat all
	your processing power in 3 easy steps
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On Fri, Aug 26, 2016 at 10:48 PM, Chad Parker
(parker DOT charles AT gmail DOT com) [via geda-user AT delorie DOT com]
<geda-user AT delorie DOT com> wrote:
> FWIW, this is something I've thought a lot about also. It would be very
> cool, but as with all simulation, to do it and get an answer out that
> actually resembles the real world is really hard. There are a lot of details
> that have to be taken into account, and then you have to make sure that your
> fab gets them all right too when you build the board. You can get maybe 10%
> variation in the dielectric constant of FR4, for example. PCB is not
> currently aware of many of those details, like board material, layer
> thickness, the amount of prepreg between the layers, etc. so you'd still
> have to add all that information in somewhere.

To do this we would have to write a geometry export engine from pcb-*
to what ever format the meshing tool used with the FEM tool uses. (in
the case of openems it is built in) FEM is all about meshing. The
geometry is meshed and then like in spice a FEM solvers build a
jacobian is and nodes in it processed. Just like in spice there are
time step errors but also, mesh type, mesh density, and boundary
conditions all of which you can get wrong and still have a valid
looking result. What I am getting at is that like spice (only more so)
it is very easy to have the program run and produce convincing but
bogus results. These draw backs are not unique to openems they are a
universal to the FEM experience. Every FEM comes with caveats about
how it's use case and people violate them all the time with out
knowing. Once worse they get blinded by how pretty the graphs are and
they believe them because of how magical it all looks.

I am in favor of this as a long term goal. I am just saying yes you
are right but the real problems with FEM are deeper than 10%
variations in FR4's dialectric from the specs nominal. Anyone doing
microwave layout would have to deal with that variation or use a
Rodgers composite (ceramic). Board material, layer thickness and etc.
are all things that we can have people define and then include in the
export. Yes they will vary in the real world but it's like anything
else the users need to account for that.

> I have a situation right now where I'm putting a couple of vias in close
> proximity to each other and counting on the parasitic capacitance to couple
> in a test signal. I'd love to be able to simulate and get an idea of what
> the capacitance actually is. I'll have to build and test it to really figure
> it out.

That is what I really care about but the parasitics are different at
different frequencies. There used to be a FDTD solver called LC issued
by Cray. Sadly Cray killed it off but I can give you the email address
of the guy who wrote it and if you ask politely he might send you a
copy. It took in gerber format and returned augmented spice netlists
with the parasitics added.

> BTW, you need more than just Hyperlynx to do this. You need the specific
> Hyperlynx 3D field solver module. My employer has licenses for MG, including
> Hyperlynx, but that module is licensed separately (I was just looking into
> this last week).

I was not saying we should add hyperlynx. Please read my other email
in this thread replying to Bert on that. The only reason hyperlynx has
come up is that one example I linked to used it with an open source
hyperlynx to openems conversion tool.

> I don't know much about gnucap, but it seems like in order to use it to
> simulate a PCB like this, you still need to be able to abstract a circuit
> model from the layout, and that's what the fancy, expensive programs do.

You are imaging something larger than I was proposing. I would like to
do what you are talking about but for a lot of people would be happy
to test if the distributed element filter they have drafted works.

> --Chad
>
> On Fri, Aug 26, 2016 at 5:15 PM, al davis <ad252 AT freeelectron DOT net> wrote:
>>
>> On Fri, 26 Aug 2016 21:45:00 +0200
>> "Bert Timmerman (bert DOT timmerman AT xs4all DOT nl) [via geda-user AT delorie DOT com]"
>> <geda-user AT delorie DOT com> wrote:
>> > So basically you wish for a Hyperlynx exporter for pcb ;-)
>>
>> Good luck getting Mentor (owner of Hyperlynx) to do that.
>>
>> What you really need is an exporter to gnucap-Verilog, or a plugin for
>> gnucap to read (and write) the pcb format.
>>
>> If somebody wants to write that gnucap plugin, I will help you do it.
>>
>



-- 
Home
http://evanfoss.googlepages.com/
Work
http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/

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