Mail Archives: geda-user/2016/03/12/12:23:25
--Apple-Mail=_8F668FD3-6A8A-479F-B0C5-C3AA91398DC8
Content-Type: multipart/mixed;
boundary="Apple-Mail=_0E902B3E-460A-4F2B-8B89-50BC3587709D"
--Apple-Mail=_0E902B3E-460A-4F2B-8B89-50BC3587709D
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain;
charset=windows-1252
On Mar 12, 2016, at 11:53 AM, Hagen SANKOWSKI =
<hsank AT nospam DOT chipforge DOT org> wrote:
> What you've seen is the lowest level of a multi-level hiearchical =
design. Toplevel has sub-schematics which are instantiated many-times =
and contains sub-schematics itself..
Ok. One problem is that you=92re not using the right IO symbols for =
hierarchy. You should be using in-1 or out-1, matching refdes of the =
symbol to the corresponding pinlabel of the symbol that represents your =
subcircuit. Here=92s a working bottom-level schematic and the symbol =
that instantiates it:
--Apple-Mail=_0E902B3E-460A-4F2B-8B89-50BC3587709D
Content-Disposition: attachment;
filename=Booster.sch
Content-Type: application/octet-stream;
name="Booster.sch"
Content-Transfer-Encoding: 7bit
v 20130925 2
C 40000 40000 0 0 0 EMBEDDEDNoqsi-title-B.sym
[
B 40000 40000 17000 11000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 54400 41500 5 10 0 0 0 0 1
graphical=1
L 52900 40600 52900 40000 15 0 0 0 -1 -1
B 49400 40000 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 49400 40700 57000 40700 15 0 0 0 -1 -1
T 50000 40500 9 10 0 1 0 0 1
date=$Date: 2009-01-11 18:02:03 $
T 53900 40500 9 10 0 1 0 0 1
rev=$Revision: 1.1 $
T 55400 40200 9 10 0 1 0 0 1
auth=$Author: jpd $
T 50200 40800 9 8 0 1 0 0 1
fname=$Source: /cvs/MIT/TESS/AE/minisys/components/symbols/Noqsi-title-B.sym,v $
T 53200 41200 9 14 0 1 0 4 1
title=TITLE
T 49500 40800 15 8 1 0 0 0 1
FILE:
T 53000 40500 15 8 1 0 0 0 1
REVISION:
T 53000 40200 15 8 1 0 0 0 1
DRAWN BY:
T 49500 40200 15 8 1 0 0 0 1
PAGE
T 51200 40200 15 8 1 0 0 0 1
OF
T 49500 41200 15 8 1 0 0 0 1
TITLE
T 49500 40500 15 8 1 0 0 0 1
DATE
B 49400 49600 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 50200 50400 9 30 1 0 0 0 1
Noqsi Aerospace, Ltd.
T 50600 50100 9 10 1 0 0 0 1
2822 South Nova Road, Pine, Colorado, USA 80470
T 51300 49500 9 10 1 0 0 0 2
+1-303-816-2756 jpd AT noqsi DOT com
T 40000 51036 9 6 1 0 0 0 1
This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. To view a copy of the license, visit https://creativecommons.org/licenses/by-sa/4.0/legalcode
]
{
T 50000 40500 5 10 1 1 0 0 1
date=20150325
T 53900 40500 5 10 1 1 0 0 1
rev=6.1
T 55400 40200 5 10 1 1 0 0 1
auth=jpd
T 50200 40800 5 8 1 1 0 0 1
fname=Booster.sch
T 53200 41200 5 14 1 1 0 4 1
title=Parallel clock current booster
}
C 47800 48000 1 180 1 EMBEDDEDpnp.sym
[
L 48000 47200 48000 47800 3 0 0 0 -1 -1
T 48400 47600 5 10 0 0 180 6 1
device=PNP_TRANSISTOR
P 47800 47500 48000 47500 1 0 0
{
T 47900 47450 5 6 1 1 180 6 1
pinnumber=1
T 47900 47450 5 6 0 0 180 6 1
pinseq=2
T 47900 47450 5 6 0 1 180 6 1
pinlabel=B
T 47900 47450 5 6 0 1 180 6 1
pintype=pas
}
P 48300 47000 48300 47200 1 0 0
{
T 48200 47150 5 6 1 1 180 6 1
pinnumber=3
T 48200 47150 5 6 0 0 180 6 1
pinseq=1
T 48200 47150 5 6 0 1 180 6 1
pinlabel=C
T 48200 47150 5 6 0 1 180 6 1
pintype=pas
}
P 48300 47800 48300 48000 1 0 1
{
T 48200 47950 5 6 1 1 180 6 1
pinnumber=2
T 48200 47950 5 6 0 0 180 6 1
pinseq=3
T 48200 47950 5 6 0 1 180 6 1
pinlabel=E
T 48200 47950 5 6 0 1 180 6 1
pintype=pas
}
L 48000 47650 48300 47800 3 0 0 0 -1 -1
L 48000 47350 48300 47200 3 0 0 0 -1 -1
L 48000 47650 48080 47731 3 0 0 0 -1 -1
L 48080 47731 48112 47662 3 0 0 0 -1 -1
L 48000 47650 48112 47662 3 0 0 0 -1 -1
T 48400 47500 8 10 0 1 180 6 1
refdes=Q?
T 48700 47200 8 10 0 0 180 6 1
footprint=UB
]
{
T 48400 47500 5 10 1 1 180 6 1
refdes=Q3
T 46800 46800 5 10 1 1 0 0 1
model-name=MMBT2907A
T 47800 48000 5 10 0 0 0 0 1
value=MMBT2907A
}
C 47800 42900 1 0 0 EMBEDDEDnpn.sym
[
L 48000 43700 48000 43100 3 0 0 0 -1 -1
T 48400 43400 5 10 0 0 0 0 1
device=NPN_TRANSISTOR
P 47800 43400 48000 43400 1 0 0
{
T 47900 43450 5 6 1 1 0 0 1
pinnumber=1
T 47900 43450 5 6 0 0 0 0 1
pinseq=2
T 47900 43450 5 6 0 1 0 0 1
pinlabel=B
T 47900 43450 5 6 0 1 0 0 1
pintype=pas
}
P 48300 43900 48300 43700 1 0 0
{
T 48200 43750 5 6 1 1 0 0 1
pinnumber=3
T 48200 43750 5 6 0 0 0 0 1
pinseq=1
T 48200 43750 5 6 0 1 0 0 1
pinlabel=C
T 48200 43750 5 6 0 1 0 0 1
pintype=pas
}
P 48300 43100 48300 42900 1 0 1
{
T 48200 42950 5 6 1 1 0 0 1
pinnumber=2
T 48200 42950 5 6 0 0 0 0 1
pinseq=3
T 48200 42950 5 6 0 1 0 0 1
pinlabel=E
T 48200 42950 5 6 0 1 0 0 1
pintype=pas
}
L 48000 43550 48300 43700 3 0 0 0 -1 -1
L 48000 43250 48300 43100 3 0 0 0 -1 -1
L 48301 43100 48203 43109 3 0 0 0 -1 -1
L 48300 43100 48231 43173 3 0 0 0 -1 -1
L 48203 43109 48231 43173 3 0 0 0 -1 -1
T 48400 43400 8 10 0 1 0 0 1
refdes=Q?
T 48600 43700 8 10 0 0 0 0 1
footprint=UB
]
{
T 48400 43400 5 10 1 1 0 0 1
refdes=Q4
T 46900 43900 5 10 1 1 0 0 1
model-name=MMBT2222A
T 47800 42900 5 10 0 0 0 0 1
value=MMBT2222A
}
C 48200 45000 1 90 0 EMBEDDEDresistor.sym
[
L 48000 45600 48200 45500 3 0 0 0 -1 -1
L 48200 45500 48000 45400 3 0 0 0 -1 -1
L 48000 45400 48200 45300 3 0 0 0 -1 -1
L 48200 45300 48000 45200 3 0 0 0 -1 -1
T 47800 45300 5 10 0 0 90 0 1
device=RESISTOR
L 48000 45600 48200 45700 3 0 0 0 -1 -1
L 48200 45700 48100 45750 3 0 0 0 -1 -1
P 48100 45900 48100 45750 1 0 0
{
T 48050 45800 5 8 0 1 90 0 1
pinnumber=2
T 48050 45800 5 8 0 0 90 0 1
pinseq=2
T 48050 45800 5 8 0 1 90 0 1
pinlabel=2
T 48050 45800 5 8 0 1 90 0 1
pintype=pas
}
P 48100 45000 48100 45152 1 0 0
{
T 48050 45100 5 8 0 1 90 0 1
pinnumber=1
T 48050 45100 5 8 0 0 90 0 1
pinseq=1
T 48050 45100 5 8 0 1 90 0 1
pinlabel=1
T 48050 45100 5 8 0 1 90 0 1
pintype=pas
}
L 48000 45201 48100 45150 3 0 0 0 -1 -1
T 47900 45200 8 10 0 1 90 0 1
refdes=R?
T 48200 45000 8 10 0 1 90 0 1
pins=2
T 48200 45000 8 10 0 1 90 0 1
class=DISCRETE
T 47600 45600 8 10 0 0 90 0 1
spec=1% 1/10W
T 47300 45900 8 10 0 0 90 0 1
footprint=0603
T 47100 45500 8 10 0 1 90 0 1
description=Resistor
]
{
T 48000 45800 5 10 1 1 180 0 1
refdes=R7
T 47700 45200 5 10 1 1 0 0 1
value=360
T 47600 45600 5 10 0 0 90 0 1
spec=5% 1/4W
T 47300 45900 5 10 0 0 90 0 1
footprint=1206
}
N 48100 45900 48100 47000 4
{
T 47800 46300 5 10 1 1 0 0 1
netname=g1
}
N 48100 47000 48300 47000 4
N 48100 45000 48100 43900 4
{
T 48200 44500 5 10 1 1 0 0 1
netname=g2
}
N 48100 43900 48300 43900 4
N 48800 43700 48800 42600 4
N 48100 42900 48800 42900 4
N 48800 47200 48800 48000 4
C 47600 48500 1 0 0 EMBEDDEDresistor.sym
[
L 48200 48700 48100 48500 3 0 0 0 -1 -1
L 48100 48500 48000 48700 3 0 0 0 -1 -1
L 48000 48700 47900 48500 3 0 0 0 -1 -1
L 47900 48500 47800 48700 3 0 0 0 -1 -1
T 47900 48900 5 10 0 0 0 0 1
device=RESISTOR
L 48200 48700 48300 48500 3 0 0 0 -1 -1
L 48300 48500 48350 48600 3 0 0 0 -1 -1
P 48500 48600 48350 48600 1 0 0
{
T 48400 48650 5 8 0 1 0 0 1
pinnumber=2
T 48400 48650 5 8 0 0 0 0 1
pinseq=2
T 48400 48650 5 8 0 1 0 0 1
pinlabel=2
T 48400 48650 5 8 0 1 0 0 1
pintype=pas
}
P 47600 48600 47752 48600 1 0 0
{
T 47700 48650 5 8 0 1 0 0 1
pinnumber=1
T 47700 48650 5 8 0 0 0 0 1
pinseq=1
T 47700 48650 5 8 0 1 0 0 1
pinlabel=1
T 47700 48650 5 8 0 1 0 0 1
pintype=pas
}
L 47801 48700 47750 48600 3 0 0 0 -1 -1
T 47800 48800 8 10 0 1 0 0 1
refdes=R?
T 47600 48500 8 10 0 1 0 0 1
pins=2
T 47600 48500 8 10 0 1 0 0 1
class=DISCRETE
T 48200 49100 8 10 0 0 0 0 1
spec=1% 1/10W
T 48500 49400 8 10 0 0 0 0 1
footprint=0603
T 48100 49600 8 10 0 1 0 0 1
description=Resistor
]
{
T 47800 48800 5 10 1 1 0 0 1
refdes=R3
T 47800 48200 5 10 1 1 0 0 1
value=3.74k
}
N 47600 48600 47600 47500 4
N 48500 48000 48500 48900 4
C 47200 42800 1 0 0 EMBEDDEDresistor.sym
[
L 47800 43000 47700 42800 3 0 0 0 -1 -1
L 47700 42800 47600 43000 3 0 0 0 -1 -1
L 47600 43000 47500 42800 3 0 0 0 -1 -1
L 47500 42800 47400 43000 3 0 0 0 -1 -1
T 47500 43200 5 10 0 0 0 0 1
device=RESISTOR
L 47800 43000 47900 42800 3 0 0 0 -1 -1
L 47900 42800 47950 42900 3 0 0 0 -1 -1
P 48100 42900 47950 42900 1 0 0
{
T 48000 42950 5 8 0 1 0 0 1
pinnumber=2
T 48000 42950 5 8 0 0 0 0 1
pinseq=2
T 48000 42950 5 8 0 1 0 0 1
pinlabel=2
T 48000 42950 5 8 0 1 0 0 1
pintype=pas
}
P 47200 42900 47352 42900 1 0 0
{
T 47300 42950 5 8 0 1 0 0 1
pinnumber=1
T 47300 42950 5 8 0 0 0 0 1
pinseq=1
T 47300 42950 5 8 0 1 0 0 1
pinlabel=1
T 47300 42950 5 8 0 1 0 0 1
pintype=pas
}
L 47401 43000 47350 42900 3 0 0 0 -1 -1
T 47400 43100 8 10 0 1 0 0 1
refdes=R?
T 47200 42800 8 10 0 1 0 0 1
pins=2
T 47200 42800 8 10 0 1 0 0 1
class=DISCRETE
T 47800 43400 8 10 0 0 0 0 1
spec=1% 1/10W
T 48100 43700 8 10 0 0 0 0 1
footprint=0603
T 47700 43900 8 10 0 1 0 0 1
description=Resistor
]
{
T 47400 43100 5 10 1 1 0 0 1
refdes=R4
T 47400 42500 5 10 1 1 0 0 1
value=3.74k
}
N 47200 42900 47200 43400 4
N 47800 47500 47000 47500 4
N 47800 43400 47000 43400 4
N 48300 48000 48800 48000 4
C 46100 47400 1 0 0 EMBEDDEDresistor.sym
[
L 46700 47600 46600 47400 3 0 0 0 -1 -1
L 46600 47400 46500 47600 3 0 0 0 -1 -1
L 46500 47600 46400 47400 3 0 0 0 -1 -1
L 46400 47400 46300 47600 3 0 0 0 -1 -1
T 46400 47800 5 10 0 0 0 0 1
device=RESISTOR
L 46700 47600 46800 47400 3 0 0 0 -1 -1
L 46800 47400 46850 47500 3 0 0 0 -1 -1
P 47000 47500 46850 47500 1 0 0
{
T 46900 47550 5 8 0 1 0 0 1
pinnumber=2
T 46900 47550 5 8 0 0 0 0 1
pinseq=2
T 46900 47550 5 8 0 1 0 0 1
pinlabel=2
T 46900 47550 5 8 0 1 0 0 1
pintype=pas
}
P 46100 47500 46252 47500 1 0 0
{
T 46200 47550 5 8 0 1 0 0 1
pinnumber=1
T 46200 47550 5 8 0 0 0 0 1
pinseq=1
T 46200 47550 5 8 0 1 0 0 1
pinlabel=1
T 46200 47550 5 8 0 1 0 0 1
pintype=pas
}
L 46301 47600 46250 47500 3 0 0 0 -1 -1
T 46300 47700 8 10 0 1 0 0 1
refdes=R?
T 46100 47400 8 10 0 1 0 0 1
pins=2
T 46100 47400 8 10 0 1 0 0 1
class=DISCRETE
T 46700 48000 8 10 0 0 0 0 1
spec=1% 1/10W
T 47000 48300 8 10 0 0 0 0 1
footprint=0603
T 46600 48500 8 10 0 1 0 0 1
description=Resistor
]
{
T 46300 47700 5 10 1 1 0 0 1
refdes=R5
T 46300 47100 5 10 1 1 0 0 1
value=3.74k
}
C 46100 43300 1 0 0 EMBEDDEDresistor.sym
[
L 46700 43500 46600 43300 3 0 0 0 -1 -1
L 46600 43300 46500 43500 3 0 0 0 -1 -1
L 46500 43500 46400 43300 3 0 0 0 -1 -1
L 46400 43300 46300 43500 3 0 0 0 -1 -1
T 46400 43700 5 10 0 0 0 0 1
device=RESISTOR
L 46700 43500 46800 43300 3 0 0 0 -1 -1
L 46800 43300 46850 43400 3 0 0 0 -1 -1
P 47000 43400 46850 43400 1 0 0
{
T 46900 43450 5 8 0 1 0 0 1
pinnumber=2
T 46900 43450 5 8 0 0 0 0 1
pinseq=2
T 46900 43450 5 8 0 1 0 0 1
pinlabel=2
T 46900 43450 5 8 0 1 0 0 1
pintype=pas
}
P 46100 43400 46252 43400 1 0 0
{
T 46200 43450 5 8 0 1 0 0 1
pinnumber=1
T 46200 43450 5 8 0 0 0 0 1
pinseq=1
T 46200 43450 5 8 0 1 0 0 1
pinlabel=1
T 46200 43450 5 8 0 1 0 0 1
pintype=pas
}
L 46301 43500 46250 43400 3 0 0 0 -1 -1
T 46300 43600 8 10 0 1 0 0 1
refdes=R?
T 46100 43300 8 10 0 1 0 0 1
pins=2
T 46100 43300 8 10 0 1 0 0 1
class=DISCRETE
T 46700 43900 8 10 0 0 0 0 1
spec=1% 1/10W
T 47000 44200 8 10 0 0 0 0 1
footprint=0603
T 46600 44400 8 10 0 1 0 0 1
description=Resistor
]
{
T 46300 43600 5 10 1 1 0 0 1
refdes=R6
T 46300 43000 5 10 1 1 0 0 1
value=3.74k
}
C 49400 45300 1 0 0 EMBEDDEDout-1.sym
[
P 49400 45400 49600 45400 1 0 0
{
T 49550 45450 5 6 0 1 0 0 1
pinnumber=1
T 49550 45450 5 6 0 0 0 0 1
pinseq=1
}
L 49600 45400 50000 45400 6 0 0 0 -1 -1
L 50000 45400 49900 45500 6 0 0 0 -1 -1
L 50000 45400 49900 45300 6 0 0 0 -1 -1
T 49400 45600 5 10 0 0 0 0 1
device=OUTPUT
T 49400 45600 8 10 0 1 0 0 1
refdes=pinlabel
]
{
T 49400 45500 5 10 1 1 0 0 1
refdes=Out
}
N 48800 45400 49400 45400 4
C 45500 47400 1 0 0 EMBEDDEDin-1.sym
[
P 45900 47500 46100 47500 1 0 1
{
T 45950 47550 5 6 0 1 0 0 1
pinnumber=1
T 45950 47550 5 6 0 0 0 0 1
pinseq=1
}
L 45600 47500 45500 47600 6 0 0 0 -1 -1
L 45600 47500 45500 47400 6 0 0 0 -1 -1
L 45900 47500 45600 47500 6 0 0 0 -1 -1
T 45500 47700 5 10 0 0 0 0 1
device=INPUT
T 45500 47700 8 10 0 1 0 0 1
refdes=pinlabel
]
{
T 45500 47700 5 10 0 0 0 0 1
device=INPUT
T 45500 47700 5 10 1 1 0 0 1
refdes=\_Low\_
}
C 45500 43300 1 0 0 EMBEDDEDin-1.sym
[
P 45900 43400 46100 43400 1 0 1
{
T 45950 43450 5 6 0 1 0 0 1
pinnumber=1
T 45950 43450 5 6 0 0 0 0 1
pinseq=1
}
L 45600 43400 45500 43500 6 0 0 0 -1 -1
L 45600 43400 45500 43300 6 0 0 0 -1 -1
L 45900 43400 45600 43400 6 0 0 0 -1 -1
T 45500 43600 5 10 0 0 0 0 1
device=INPUT
T 45500 43600 8 10 0 1 0 0 1
refdes=pinlabel
]
{
T 45500 43600 5 10 0 0 0 0 1
device=INPUT
T 45500 43600 5 10 1 1 0 0 1
refdes=High
}
C 48400 49500 1 270 0 EMBEDDEDin-1.sym
[
P 48500 49100 48500 48900 1 0 1
{
T 48550 49050 5 6 0 1 270 0 1
pinnumber=1
T 48550 49050 5 6 0 0 270 0 1
pinseq=1
}
L 48500 49400 48600 49500 6 0 0 0 -1 -1
L 48500 49400 48400 49500 6 0 0 0 -1 -1
L 48500 49100 48500 49400 6 0 0 0 -1 -1
T 48700 49500 5 10 0 0 270 0 1
device=INPUT
T 48700 49500 8 10 0 1 270 0 1
refdes=pinlabel
]
{
T 48700 49500 5 10 0 0 270 0 1
device=INPUT
T 48600 49100 5 10 1 1 0 0 1
refdes=V+
}
C 48900 42000 1 90 0 EMBEDDEDin-1.sym
[
P 48800 42400 48800 42600 1 0 1
{
T 48750 42450 5 6 0 1 90 0 1
pinnumber=1
T 48750 42450 5 6 0 0 90 0 1
pinseq=1
}
L 48800 42100 48700 42000 6 0 0 0 -1 -1
L 48800 42100 48900 42000 6 0 0 0 -1 -1
L 48800 42400 48800 42100 6 0 0 0 -1 -1
T 48600 42000 5 10 0 0 90 0 1
device=INPUT
T 48600 42000 8 10 0 1 90 0 1
refdes=pinlabel
]
{
T 48600 42000 5 10 0 0 90 0 1
device=INPUT
T 48700 42400 5 10 1 1 180 0 1
refdes=V-
}
C 41300 45000 1 0 0 EMBEDDEDBooster.sym
[
P 42900 45600 42600 45600 1 0 0
{
T 42695 45645 5 8 0 1 0 0 1
pinnumber=2
T 42700 45550 5 8 0 1 0 2 1
pinseq=2
T 42445 45595 9 8 1 1 0 7 1
pinlabel=Out
T 42550 45600 5 8 0 1 0 8 1
pintype=pas
}
P 41300 45300 41600 45300 1 0 0
{
T 41500 45350 5 8 0 1 0 6 1
pinnumber=3
T 41500 45250 5 8 0 1 0 8 1
pinseq=3
T 41650 45300 9 8 1 1 0 1 1
pinlabel=\_Low\_
T 41650 45300 5 8 0 1 0 2 1
pintype=pas
}
P 42100 46200 42100 45900 1 0 0
{
T 42150 46050 5 8 0 1 0 0 1
pinnumber=7
T 42150 46050 5 8 0 1 0 2 1
pinseq=7
T 42100 45850 9 8 1 1 0 5 1
pinlabel=V+
T 42100 45700 5 8 0 1 0 5 1
pintype=pwr
}
P 42100 45000 42100 45300 1 0 0
{
T 42150 45100 5 8 0 1 0 0 1
pinnumber=9
T 42150 45100 5 8 0 1 0 2 1
pinseq=9
T 42100 45350 9 8 1 1 0 3 1
pinlabel=V-
T 42100 45500 5 8 0 1 0 3 1
pintype=pwr
}
P 41300 45900 41600 45900 1 0 0
{
T 41505 45945 5 8 0 1 0 6 1
pinnumber=11
T 41500 45850 5 8 0 1 0 8 1
pinseq=11
T 41655 45895 9 8 1 1 0 1 1
pinlabel=High
T 41650 45900 5 8 0 1 0 2 1
pintype=pas
}
T 42400 45800 5 10 0 1 0 0 1
refdes=X?
T 41600 46800 5 10 0 0 0 0 1
device=Booster
T 41600 47000 5 10 0 0 0 0 1
author=jpd AT noqsi DOT com
T 41600 47200 5 10 0 0 0 0 1
description=Parallel clock current booster
T 41600 47400 5 10 0 0 0 0 1
numslots=0
T 41600 47600 8 10 0 0 0 0 1
source=Booster.sch
L 41600 46200 41600 45000 3 0 0 0 -1 -1
L 41600 45000 42600 45600 3 0 0 0 -1 -1
L 42600 45600 41600 46200 3 0 0 0 -1 -1
T 41700 45600 9 6 1 0 0 1 1
Booster
T 41600 46600 8 10 0 0 0 0 1
spice-prototype=X? %down Booster
]
{
T 42400 45800 5 10 1 1 0 0 1
refdes=X?
T 41300 45000 5 10 0 0 0 0 1
graphical=1
}
T 50700 40200 9 10 1 0 0 0 1
1
T 51700 40200 9 10 1 0 0 0 1
1
N 48800 44500 48800 46400 4
C 48300 43700 1 0 0 EMBEDDEDNMOS.sym
[
T 48900 44200 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
T 48900 44200 5 10 0 0 0 0 1
numslots=0
T 48900 44200 5 10 0 0 0 0 1
description=generic N channel MOS transistor (enhancement type)
L 48550 44300 48800 44300 3 0 0 0 -1 -1
L 48550 43900 48800 43900 3 0 0 0 -1 -1
L 48550 44100 48650 44150 3 0 0 0 -1 -1
L 48550 44100 48650 44050 3 0 0 0 -1 -1
P 48300 43900 48500 43900 1 0 0
{
T 48300 44000 5 10 0 1 0 0 1
pinnumber=4
T 48300 44000 9 10 0 1 0 0 1
pinlabel=G
T 48300 44000 5 10 0 0 0 0 1
pinseq=4
T 48300 44000 5 10 0 0 0 0 1
pintype=pas
}
P 48800 44300 48800 44500 1 0 1
{
T 48600 44400 5 10 0 1 0 0 1
pinnumber=15
T 48600 44400 9 10 0 1 0 0 1
pinlabel=D
T 48600 44400 5 10 0 0 0 0 1
pinseq=15
T 48600 44400 5 10 0 0 0 0 1
pintype=pas
}
P 48800 43900 48800 43700 1 0 1
{
T 48600 43700 5 10 0 1 0 0 1
pinnumber=6
T 48600 43700 9 10 0 1 0 0 1
pinlabel=S
T 48600 43700 5 10 0 0 0 0 1
pinseq=6
T 48600 43700 5 10 0 0 0 0 1
pintype=pas
}
T 49000 44300 8 10 0 1 0 0 1
refdes=Q?
L 48550 44375 48550 44225 3 0 0 0 -1 -1
L 48550 44175 48550 44025 3 0 0 0 -1 -1
L 48550 43975 48550 43825 3 0 0 0 -1 -1
L 48500 44300 48500 43900 3 0 0 0 -1 -1
L 48550 44100 48700 44100 3 0 0 0 -1 -1
L 48700 44100 48700 43900 3 0 0 0 -1 -1
T 48500 45300 5 10 0 0 0 0 1
footprint=18LCC
T 48500 45100 5 10 0 0 0 0 1
spice-prototype=X? #1 #4 #6 model-name@
T 48500 44900 5 10 0 0 0 0 1
model-name=irfru220n
T 48500 44700 5 10 0 0 0 0 1
value=IRFE220
P 48800 43900 48800 43700 1 0 1
{
T 48600 43700 5 10 0 1 0 0 1
pinnumber=7
T 48600 43700 9 10 0 1 0 0 1
pinlabel=S
T 48600 43700 5 10 0 0 0 0 1
pinseq=7
T 48600 43700 5 10 0 0 0 0 1
pintype=pas
}
P 48800 43900 48800 43700 1 0 1
{
T 48600 43700 5 10 0 1 0 0 1
pinnumber=8
T 48600 43700 9 10 0 1 0 0 1
pinlabel=S
T 48600 43700 5 10 0 0 0 0 1
pinseq=8
T 48600 43700 5 10 0 0 0 0 1
pintype=pas
}
P 48800 43900 48800 43700 1 0 1
{
T 48600 43700 5 10 0 1 0 0 1
pinnumber=9
T 48600 43700 9 10 0 1 0 0 1
pinlabel=S
T 48600 43700 5 10 0 0 0 0 1
pinseq=9
T 48600 43700 5 10 0 0 0 0 1
pintype=pas
}
P 48800 43900 48800 43700 1 0 1
{
T 48600 43700 5 10 0 1 0 0 1
pinnumber=10
T 48600 43700 9 10 0 1 0 0 1
pinlabel=S
T 48600 43700 5 10 0 0 0 0 1
pinseq=10
T 48600 43700 5 10 0 0 0 0 1
pintype=pas
}
P 48800 43900 48800 43700 1 0 1
{
T 48600 43700 5 10 0 1 0 0 1
pinnumber=11
T 48600 43700 9 10 0 1 0 0 1
pinlabel=S
T 48600 43700 5 10 0 0 0 0 1
pinseq=11
T 48600 43700 5 10 0 0 0 0 1
pintype=pas
}
P 48800 43900 48800 43700 1 0 1
{
T 48600 43700 5 10 0 1 0 0 1
pinnumber=12
T 48600 43700 9 10 0 1 0 0 1
pinlabel=S
T 48600 43700 5 10 0 0 0 0 1
pinseq=12
T 48600 43700 5 10 0 0 0 0 1
pintype=pas
}
P 48800 43900 48800 43700 1 0 1
{
T 48600 43700 5 10 0 1 0 0 1
pinnumber=13
T 48600 43700 9 10 0 1 0 0 1
pinlabel=S
T 48600 43700 5 10 0 0 0 0 1
pinseq=13
T 48600 43700 5 10 0 0 0 0 1
pintype=pas
}
P 48800 44300 48800 44500 1 0 1
{
T 48600 44400 5 10 0 1 0 0 1
pinnumber=16
T 48600 44400 9 10 0 1 0 0 1
pinlabel=D
T 48600 44400 5 10 0 0 0 0 1
pinseq=16
T 48600 44400 5 10 0 0 0 0 1
pintype=pas
}
P 48800 44300 48800 44500 1 0 1
{
T 48600 44400 5 10 0 1 0 0 1
pinnumber=17
T 48600 44400 9 10 0 1 0 0 1
pinlabel=D
T 48600 44400 5 10 0 0 0 0 1
pinseq=17
T 48600 44400 5 10 0 0 0 0 1
pintype=pas
}
P 48800 44300 48800 44500 1 0 1
{
T 48600 44400 5 10 0 1 0 0 1
pinnumber=18
T 48600 44400 9 10 0 1 0 0 1
pinlabel=D
T 48600 44400 5 10 0 0 0 0 1
pinseq=18
T 48600 44400 5 10 0 0 0 0 1
pintype=pas
}
P 48800 44300 48800 44500 1 0 1
{
T 48600 44400 5 10 0 1 0 0 1
pinnumber=1
T 48600 44400 9 10 0 1 0 0 1
pinlabel=D
T 48600 44400 5 10 0 0 0 0 1
pinseq=1
T 48600 44400 5 10 0 0 0 0 1
pintype=pas
}
P 48800 44300 48800 44500 1 0 1
{
T 48600 44400 5 10 0 1 0 0 1
pinnumber=2
T 48600 44400 9 10 0 1 0 0 1
pinlabel=D
T 48600 44400 5 10 0 0 0 0 1
pinseq=2
T 48600 44400 5 10 0 0 0 0 1
pintype=pas
}
P 48300 43900 48500 43900 1 0 0
{
T 48300 44000 5 10 0 1 0 0 1
pinnumber=5
T 48300 44000 9 10 0 1 0 0 1
pinlabel=G
T 48300 44000 5 10 0 0 0 0 1
pinseq=5
T 48300 44000 5 10 0 0 0 0 1
pintype=pas
}
T 48500 45700 8 10 0 0 0 0 1
pins=18
T 48500 45500 8 10 0 0 0 0 1
pins-used=16
]
{
T 49000 44300 5 10 1 1 0 0 1
refdes=Q2
}
C 48300 47200 1 180 1 EMBEDDEDPMOS.sym
[
T 48900 46700 5 10 0 0 180 6 1
device=PMOS_TRANSISTOR
T 48900 46700 5 10 0 0 180 6 1
numslots=0
T 48900 46700 5 10 0 0 180 6 1
description=generic P channel MOS transistor (enhancement type)
L 48550 46600 48800 46600 3 0 0 0 -1 -1
L 48550 47000 48800 47000 3 0 0 0 -1 -1
L 48600 46850 48700 46800 3 0 0 0 -1 -1
L 48600 46750 48700 46800 3 0 0 0 -1 -1
T 49000 46600 8 10 0 1 180 6 1
refdes=Q?
L 48550 46525 48550 46675 3 0 0 0 -1 -1
L 48550 46725 48550 46875 3 0 0 0 -1 -1
L 48550 46925 48550 47075 3 0 0 0 -1 -1
L 48500 46600 48500 47000 3 0 0 0 -1 -1
L 48550 46800 48700 46800 3 0 0 0 -1 -1
L 48700 46800 48700 47000 3 0 0 0 -1 -1
T 48800 46100 5 10 0 0 180 6 1
model-name=irfr9120n
T 48800 46300 5 10 0 0 180 6 1
value=IRFE9120
P 48300 47000 48500 47000 1 0 0
{
T 48300 46900 5 10 0 1 180 6 1
pinnumber=4
T 48300 46900 9 10 0 1 180 6 1
pinlabel=G
T 48300 46900 5 10 0 0 180 6 1
pinseq=4
T 48300 46900 5 10 0 0 180 6 1
pintype=pas
}
P 48800 46600 48800 46400 1 0 1
{
T 48600 46500 5 10 0 1 180 6 1
pinnumber=15
T 48600 46500 9 10 0 1 180 6 1
pinlabel=D
T 48600 46500 5 10 0 0 180 6 1
pinseq=15
T 48600 46500 5 10 0 0 180 6 1
pintype=pas
}
P 48800 47000 48800 47200 1 0 1
{
T 48600 47200 5 10 0 1 180 6 1
pinnumber=6
T 48600 47200 9 10 0 1 180 6 1
pinlabel=S
T 48600 47200 5 10 0 0 180 6 1
pinseq=6
T 48600 47200 5 10 0 0 180 6 1
pintype=pas
}
P 48800 47000 48800 47200 1 0 1
{
T 48600 47200 5 10 0 1 180 6 1
pinnumber=7
T 48600 47200 9 10 0 1 180 6 1
pinlabel=S
T 48600 47200 5 10 0 0 180 6 1
pinseq=7
T 48600 47200 5 10 0 0 180 6 1
pintype=pas
}
P 48800 47000 48800 47200 1 0 1
{
T 48600 47200 5 10 0 1 180 6 1
pinnumber=8
T 48600 47200 9 10 0 1 180 6 1
pinlabel=S
T 48600 47200 5 10 0 0 180 6 1
pinseq=8
T 48600 47200 5 10 0 0 180 6 1
pintype=pas
}
P 48800 47000 48800 47200 1 0 1
{
T 48600 47200 5 10 0 1 180 6 1
pinnumber=9
T 48600 47200 9 10 0 1 180 6 1
pinlabel=S
T 48600 47200 5 10 0 0 180 6 1
pinseq=9
T 48600 47200 5 10 0 0 180 6 1
pintype=pas
}
P 48800 47000 48800 47200 1 0 1
{
T 48600 47200 5 10 0 1 180 6 1
pinnumber=10
T 48600 47200 9 10 0 1 180 6 1
pinlabel=S
T 48600 47200 5 10 0 0 180 6 1
pinseq=10
T 48600 47200 5 10 0 0 180 6 1
pintype=pas
}
P 48800 47000 48800 47200 1 0 1
{
T 48600 47200 5 10 0 1 180 6 1
pinnumber=11
T 48600 47200 9 10 0 1 180 6 1
pinlabel=S
T 48600 47200 5 10 0 0 180 6 1
pinseq=11
T 48600 47200 5 10 0 0 180 6 1
pintype=pas
}
P 48800 47000 48800 47200 1 0 1
{
T 48600 47200 5 10 0 1 180 6 1
pinnumber=12
T 48600 47200 9 10 0 1 180 6 1
pinlabel=S
T 48600 47200 5 10 0 0 180 6 1
pinseq=12
T 48600 47200 5 10 0 0 180 6 1
pintype=pas
}
P 48800 47000 48800 47200 1 0 1
{
T 48600 47200 5 10 0 1 180 6 1
pinnumber=13
T 48600 47200 9 10 0 1 180 6 1
pinlabel=S
T 48600 47200 5 10 0 0 180 6 1
pinseq=13
T 48600 47200 5 10 0 0 180 6 1
pintype=pas
}
P 48800 46600 48800 46400 1 0 1
{
T 48600 46500 5 10 0 1 180 6 1
pinnumber=16
T 48600 46500 9 10 0 1 180 6 1
pinlabel=D
T 48600 46500 5 10 0 0 180 6 1
pinseq=16
T 48600 46500 5 10 0 0 180 6 1
pintype=pas
}
P 48800 46600 48800 46400 1 0 1
{
T 48600 46500 5 10 0 1 180 6 1
pinnumber=17
T 48600 46500 9 10 0 1 180 6 1
pinlabel=D
T 48600 46500 5 10 0 0 180 6 1
pinseq=17
T 48600 46500 5 10 0 0 180 6 1
pintype=pas
}
P 48800 46600 48800 46400 1 0 1
{
T 48600 46500 5 10 0 1 180 6 1
pinnumber=18
T 48600 46500 9 10 0 1 180 6 1
pinlabel=D
T 48600 46500 5 10 0 0 180 6 1
pinseq=18
T 48600 46500 5 10 0 0 180 6 1
pintype=pas
}
P 48800 46600 48800 46400 1 0 1
{
T 48600 46500 5 10 0 1 180 6 1
pinnumber=1
T 48600 46500 9 10 0 1 180 6 1
pinlabel=D
T 48600 46500 5 10 0 0 180 6 1
pinseq=1
T 48600 46500 5 10 0 0 180 6 1
pintype=pas
}
P 48800 46600 48800 46400 1 0 1
{
T 48600 46500 5 10 0 1 180 6 1
pinnumber=2
T 48600 46500 9 10 0 1 180 6 1
pinlabel=D
T 48600 46500 5 10 0 0 180 6 1
pinseq=2
T 48600 46500 5 10 0 0 180 6 1
pintype=pas
}
P 48300 47000 48500 47000 1 0 0
{
T 48300 46900 5 10 0 1 180 6 1
pinnumber=5
T 48300 46900 9 10 0 1 180 6 1
pinlabel=G
T 48300 46900 5 10 0 0 180 6 1
pinseq=5
T 48300 46900 5 10 0 0 180 6 1
pintype=pas
}
T 48800 45700 5 10 0 0 180 6 1
footprint=18LCC
T 48800 45900 5 10 0 0 180 6 1
spice-prototype=X? #1 #4 #6 model-name@
T 48800 45300 8 10 0 0 180 6 1
pins=18
T 48800 45500 8 10 0 0 180 6 1
pins-used=16
]
{
T 49000 46600 5 10 1 1 180 6 1
refdes=Q1
}
T 41200 44400 8 10 1 1 0 0 1
spice-prolog=.subckt Booster %up
--Apple-Mail=_0E902B3E-460A-4F2B-8B89-50BC3587709D
Content-Disposition: attachment;
filename=Booster.sym
Content-Type: application/octet-stream;
name="Booster.sym"
Content-Transfer-Encoding: 7bit
v 20130925 2
P 1600 600 1300 600 1 0 0
{
T 1395 645 5 8 0 1 0 0 1
pinnumber=2
T 1400 550 5 8 0 1 0 2 1
pinseq=2
T 1145 595 9 8 1 1 0 7 1
pinlabel=Out
T 1250 600 5 8 0 1 0 8 1
pintype=pas
}
P 0 300 300 300 1 0 0
{
T 200 350 5 8 0 1 0 6 1
pinnumber=3
T 200 250 5 8 0 1 0 8 1
pinseq=3
T 350 300 9 8 1 1 0 1 1
pinlabel=\_Low\_
T 350 300 5 8 0 1 0 2 1
pintype=pas
}
P 800 1200 800 900 1 0 0
{
T 850 1050 5 8 0 1 0 0 1
pinnumber=7
T 850 1050 5 8 0 1 0 2 1
pinseq=7
T 800 850 9 8 1 1 0 5 1
pinlabel=V+
T 800 700 5 8 0 1 0 5 1
pintype=pwr
}
P 800 0 800 300 1 0 0
{
T 850 100 5 8 0 1 0 0 1
pinnumber=9
T 850 100 5 8 0 1 0 2 1
pinseq=9
T 800 350 9 8 1 1 0 3 1
pinlabel=V-
T 800 500 5 8 0 1 0 3 1
pintype=pwr
}
P 0 900 300 900 1 0 0
{
T 205 945 5 8 0 1 0 6 1
pinnumber=11
T 200 850 5 8 0 1 0 8 1
pinseq=11
T 355 895 9 8 1 1 0 1 1
pinlabel=High
T 350 900 5 8 0 1 0 2 1
pintype=pas
}
T 1100 800 5 10 1 1 0 0 1
refdes=X?
T 300 1800 5 10 0 0 0 0 1
device=Booster
T 300 2000 5 10 0 0 0 0 1
author=jpd AT noqsi DOT com
T 300 2200 5 10 0 0 0 0 1
description=Parallel clock current booster
T 300 2400 5 10 0 0 0 0 1
numslots=0
T 300 2600 8 10 0 0 0 0 1
source=Booster.sch
L 300 1200 300 0 3 0 0 0 -1 -1
L 300 0 1300 600 3 0 0 0 -1 -1
L 1300 600 300 1200 3 0 0 0 -1 -1
T 400 600 9 6 1 0 0 1 1
Booster
T 300 1600 8 10 0 0 0 0 1
spice-prototype=X? %down Booster
--Apple-Mail=_0E902B3E-460A-4F2B-8B89-50BC3587709D
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain;
charset=windows-1252
I see no point to your netname attributes unless you=92re making a =
hierarchical netlist (which pcb cannot use). Your nets will get renamed =
to their names in the higher level schematic.
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
--Apple-Mail=_0E902B3E-460A-4F2B-8B89-50BC3587709D--
--Apple-Mail=_8F668FD3-6A8A-479F-B0C5-C3AA91398DC8
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename=signature.asc
Content-Type: application/pgp-signature;
name=signature.asc
Content-Description: Message signed with OpenPGP using GPGMail
-----BEGIN PGP SIGNATURE-----
Comment: GPGTools - https://gpgtools.org
iQIcBAEBCgAGBQJW5FBvAAoJEF1Aj/0UKykRyX0P/1l4hI0p79q7JdeySZDnJSnR
yT20rlqm9ujfrY0/8y5qYmTZKIc+3ttnYHooCmAFBDNGkP+qBiBxER9SZTpA1ln1
UWdjZrnAvQSaLuuPzs1aYBKMCbYliEi42YVkqrdePcv9vU0jVA4QMqL3Dv6X91VM
wQGdoOYST35WBM58O/LBP/0OKMHVbrpSVO7I4jUuidiXiF89Up52H5IhXEDTiwJg
0awck77z0ct5lqAi6N4/61BPa+ZJijfk8B9TngFHdcqM9saNW9X0vTTc95GjRJxr
0XGqlRnnlVBwrfowPWMdheX/a1NpMRlQqnp7wfIQE8Yc1ePmPYt2An5pEWO18Cgc
YBMh2VcSGiuyK7wk5vyuGkCbU2K1p0A4WqzWjHsol3ttTxBwsm0jtRrV3vv8Lnk/
IzBvhgZMggxYi9htMyUrobOMQE4Ry/IcmpMD5KkL6efewLC4pwDksHnKD6UqTJ0G
FDEKY1GvelK1fJODmuq074u7Pd01eMxiFSFyeJksaV1hPhe9/QvwoxhaBx/zKL3B
NENmaYDwzNrm8V/+U6bmjlFORO5gl44AKd9DBJdqU3FO17mjmuCf3Pp7bXR5DQ3v
B3YEY78cCCk8oOOiejQRvdomznpuxtAXF46QuI18SJ28AxBpnJdziXKBGxK8qeX1
G9NFZsT/1uOV1WttNoRS
=FhCV
-----END PGP SIGNATURE-----
--Apple-Mail=_8F668FD3-6A8A-479F-B0C5-C3AA91398DC8--
- Raw text -