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Mail Archives: geda-user/2016/03/01/10:57:15

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Subject: Re: [geda-user] Gnucap and Google summer of code
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From: John Doty <jpd AT noqsi DOT com>
In-Reply-To: <20160301095333.1cee2433@floyd.freeelectron.net>
Date: Tue, 1 Mar 2016 08:56:40 -0700
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References: <20160229155407 DOT 5f14a970 AT floyd DOT freeelectron DOT net> <FB047616-EDA8-4208-8F84-C9576E8D2569 AT noqsi DOT com> <20160229211820 DOT 623549f9 AT floyd DOT freeelectron DOT net> <alpine DOT DEB DOT 2 DOT 11 DOT 1603011200390 DOT 1874 AT nimbus> <20160301095333 DOT 1cee2433 AT floyd DOT freeelectron DOT net>
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On Mar 1, 2016, at 7:53 AM, al davis <ad252 AT freeelectron DOT net> wrote:

> On Tue, 1 Mar 2016 12:00:43 +0100 (CET)
> Roland Lutz <rlutz AT hedmen DOT org> wrote:
>=20
>> On Mon, 29 Feb 2016, al davis wrote:
>>> We have a start for the existing geda format, not complete, but =
already
>>> more than gnetlist does.
>>=20
>> What functionality exactly do you need which gnetlist doesn't =
provide?
>>=20
>> Maybe it's worth adding it to gnetlist so other backends can benefit =
from
>> it, too.
>=20
> Just looking at the spice netlisters:
>=20
> Import, back-annotation.

They are exporters. These things are not their province.

>=20
> Support for all symbols.

What do you mean by that?

>=20
>=20
>=20
> Looking beyond that, all that plus:
>=20
> Verilog, VHDL completeness.
>=20
> To/from other schematic formats (Kicad, Qucs).

Difficult. For flat netlists, there is a common understanding of what =
the underlying abstraction is. The problem is mostly encoding (with a =
few oddities like instance parameters in SPICE). For schematics, there =
is no such general understanding.

>=20
> Layout formats (PCB).
>=20
> Nets as first class objects.
>=20

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com



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