Mail Archives: geda-user/2016/01/26/16:24:13
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On Jan 26, 2016, at 1:54 PM, Britton Kerin (britton DOT kerin AT gmail DOT com) =
[via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:
> How exactly do you propose that they draw the hole plating that makes
> it a via, short of 3D CAD? How to limit it's layer span? You can
> draw whatever you want on layers, it just doesn't get you what you
> want. Submerged pads or insulation drawing won't get you what you
> want either.
> Either some special codes have to know what via means wrt layers, or
> you need general 3D CAD.
This is correct. Pure 2D layers are not quite good enough. I do, =
however, think that 2D with a few special exceptions should suffice for =
printed circuits. The fundamental problem with pcb as it exists is that =
it=92s a tangle of special exceptions without a clean concept of layer =
underneath.
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
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