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Fri, 22 Jan 2016 01:04:02 -0800 (PST) | |
Date: | Fri, 22 Jan 2016 10:03:57 +0100 |
From: | "Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> |
To: | geda-user AT delorie DOT com |
Subject: | Re: [geda-user] PCB data structures (was: features: layers stack, |
padstack/vias) | |
Message-Id: | <20160122100357.25d0bc2399d07d257143456a@gmail.com> |
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number of pcb_layer objects--which in turn contain the geometric primitives--and pcb_element objects which aren't associated with a layer. Objects of type pcb_polygon can have child objects of type pcb_polygon_hole: > > > > pcb_layout > > +- pcb_layer > > +- pcb_arc > > +- pcb_line > > +- pcb_pad > > +- pcb_pin > > +- pcb_polygon > > +- pcb_polygon_hole > > +- pcb_rat > > +- pcb_text > > +- pcb_via > > +- pcb_element > > Sounds reasonable, and similar to what we have now but with much cleaned up > naming and hierarchy. Everyon may know about it already but I forgot. If there are drawing primitives: line, arc, circle, polygon and cut out these on any layer. DRC clearance test check for interection of a grown/bloated by clearance value copy for each clearance value against each other net. Connection thru flooded copper make a cutout by a copy grown by appropriate clearance fot the nets. Nicklas Karlsson
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