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Subject:	Re: [geda-user] first attempt at bus support in gnetlist for pcb
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From:	John Griessen <john AT ecosensory DOT com>
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Date:	Sat, 16 Jan 2016 19:12:46 -0600
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On 01/16/2016 03:18 PM, John Doty wrote:
> What do you expect? For Verilog, you can connect whole busses between levels, so you want that, but you may need to translate the bus syntax. For SPICE, you can’t connect busses between levels, so you have to expand busses looking upward and downward. Upward is yet a different beast. At least SPICE isn’t fussy about naming.
Thanks for this helpful analysis of netlisting wants from a chip design and board design perspective merged.
It's just what I would have said, except I'm busy with other stuff.

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