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Subject:	Re: [geda-user] first attempt at bus support in gnetlist for pcb
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From:	John Doty <jpd AT noqsi DOT com>
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Date:	Sat, 16 Jan 2016 16:19:47 -0700
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On Jan 16, 2016, at 3:11 PM, DJ Delorie <dj AT delorie DOT com> wrote:

>=20
>> By default, a net nBL,A[8:2] internal to a subcircuit with refdes A1
>> will get the name A1/nBL,A[8:2] when gnetlist flattens
>> hierarchy. That won't expand right. And note that the user can
>> decide to use a different separator and whether hierarchy is prefix
>> or postfix in gnetlistrc, so it isn't as simple as looking for the
>> last /.
>=20
> Hmmm... so introducing the <> syntax, either explicitly or as part of
> the netlisting, gives us a foo/<a,b,c> -> foo/a,foo/b,foo/c path?

That=92s the idea.

>=20
> I think my [] syntax could be made nestable, and expanded to include
> <> or () pairings.  Perhaps the netlister could auto-wrap everything
> in a sub-circuit, then expand everything back up.

Not quite sure what you mean here. The back end and plug in have no =
control of hierarchical expansion.

>=20
> In the case where we *don't* flatten, we can still expand busses on
> either side of the boundary, but I don't know how that affects the
> net-matching mechanism in gnetlist to stitch the heirarchy together.

For hierarchical SPICE, we separately netlist the modules, so it=92s =
SPICE that notices if the definition and the instance match.

>=20
>>> Sigh.
>>=20
>> What do you expect?
>=20
> Just sighing because it's yet another not-easy-to-do-generically
> problem.
>=20

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com



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