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Date:	Sat, 16 Jan 2016 19:19:27 +0000
From:	"M. J. Everitt (m DOT j DOT everitt AT iee DOT org) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] first attempt at bus support in gnetlist for pcb
References:	<201601080714 DOT u087Ejj5032766 AT envy DOT delorie DOT com> <F723B760-53BB-467C-8595-20EB5FC50E47 AT noqsi DOT com>
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Reply-To:	geda-user AT delorie DOT com

On 16/01/16 19:03, John Doty wrote:
> Been playing around with this as a general-purpose plug in for more than just a subset of gpcb flows. Difficulties:
>
> 1. For netlists flattened by gnetlist, we have a configurable syntax for net renaming before the Scheme stuff gets the data. The bus syntax here will have some difficulty with that.
>
> 2. For genuinely hierarchical netlists, there’s probably not a single one-size-fits-all plug in solution. Not today.
>
> 3. For pinseq-centered netlisting (SPICE), it needs to expand pinseqs, too.
>
> Another issue is that “-“ seems a little strange as a range token. “:” would match Verilog and some programming languages for more user familiarity.
I think "-" dash works as a human-readable token. I'm not sure many
people would directly understand what 8:1 means - that could potentially
mean section 8 paragraph 1 or many other things (taken out of context, I
appreciate). I don't know many programs that have difficulty with this
syntax, think of printing multiple (but not All) pages from a document -
the print dialog easily handles pages 1-3,5,7-9 etc ...
> I suggest using Dirac-style angle brackets to designate a bus definition, so a typical example might be "<nBL,A[8:2]>”. While I think a sufficiently aware gnetlist plugin could navigate this without the extra tokens, we’ve historically exploited the transparency of our formats to process schematics with other tools as well. The extra tokens will help.
>
> On Jan 8, 2016, at 12:14 AM, DJ Delorie <dj AT delorie DOT com> wrote:
>
>> http://www.delorie.com/pcb/gnet-pcbfwd-bus.scm
>>
>> This is a replacement for gnet-pcbfwd.scm which PCB's File->Import uses.
>>
>> (If the scheme coding itself bothers you, you may use that as an
>> argument in the scheme debate - whether for or against is up to you.
>> Keep in mind this took me many nights to figure out :-))
>>
>> It expands lists in netnames and pin numbers like this:
>>
>> 4-7 becomes 4,5,6,7
>> 7-4 becomes 7,6,5,4
>>
>> -then-
>>
>> sym[1,2,3] becomes sym1,sym2,sym3
>>
>> -then-
>>
>> assignments between lists of netnames to lists of pinnumbers are
>> matched up one-to-one.
>>
>> assignments between one netname and a list of pinnumbers are matched
>> up one-to-many.
>>
>> Likewise for pin numbers and pin labels.
>>
>> The net result of this is that you can assign a net named "nBL,A[8-2]" to
>> a pin labelled "A[0-7]" and numbered "1-4,10-7" and they'll all get
>> hooked up as appropriate.
>>
>> You can also have a pin named "GND" and numbered "1,15,18" connected
>> to net "GND" and it will connect all three pins to the one net.
>>
>>
>> Constructive feedback welcome!
>>
>> DJ
>>
> John Doty              Noqsi Aerospace, Ltd.
> http://www.noqsi.com/
> jpd AT noqsi DOT com
>
>

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