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	Mon, 11 Jan 2016 00:41:50 -0800 (PST)
Date:	Mon, 11 Jan 2016 09:41:44 +0100
From:	"Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] Primitive electrical types --> layers
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> > >   3. For board outline is a good idea to use a filled polygon instead of a line?
> > >   4. For a board howto draw a slit? Cutout in outline polygon?
> > 
> > My board vendors reliably mill my boards by the outline gerber, with
> > lines on the outline. 
> 
> Same here. A global outline that indicates where there is some material
> is useful. Actually my preferred board house wants them drawn with a 1µ
> line width, which always makes DRC complain. So one of my feature request 
> would be to not run DRC on outline layers, or have per layer DRC rule,
> which is a good idea anyway (rules may depend on copper thickness which
> can be different on different layers).
> 
> > Did anybody had boards made where the outline was
> > specified as a polygon?
> 
> Not me.
> 
>     Gabriel

A polygon might still make sense and let exporter solve the outline problem. Do you know how they want cut outs drawn?

DRC for outline which is manufactured of insulating board must be different than for other layers. I guess minimum internal radius for the milling would the limiting factor.


Nicklas Karlsson

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