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Date:	Mon, 11 Jan 2016 09:02:28 +0100
From:	"Gabriel Paubert (paubert AT iram DOT es) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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Subject:	Re: [geda-user] Primitive electrical types --> layers
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On Mon, Jan 11, 2016 at 12:03:18AM +0100, Stephan Böttcher wrote:
> "Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via
> geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> writes:
> 
> >   3. For board outline is a good idea to use a filled polygon instead of a line?
> >   4. For a board howto draw a slit? Cutout in outline polygon?
> 
> My board vendors reliably mill my boards by the outline gerber, with
> lines on the outline. 

Same here. A global outline that indicates where there is some material
is useful. Actually my preferred board house wants them drawn with a 1µ
line width, which always makes DRC complain. So one of my feature request 
would be to not run DRC on outline layers, or have per layer DRC rule,
which is a good idea anyway (rules may depend on copper thickness which
can be different on different layers).

> Did anybody had boards made where the outline was
> specified as a polygon?

Not me.

    Gabriel

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