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Date:	Fri, 8 Jan 2016 13:31:03 -0500
Message-Id:	<201601081831.u08IV3bf029438@envy.delorie.com>
From:	DJ Delorie <dj AT delorie DOT com>
To:	geda-user AT delorie DOT com
In-reply-to:
	<CAJXU7q8ebvSPZ-sYrTcSd+0qWeGs5ZEzQAC2NNP9Qg8+ObU=8A AT mail DOT gmail DOT com>
	(geda-user AT delorie DOT com)
Subject:	Re: [geda-user] first attempt at bus support in gnetlist for pcb
References:	<201601080714 DOT u087Ejj5032766 AT envy DOT delorie DOT com> <CAJXU7q8ebvSPZ-sYrTcSd+0qWeGs5ZEzQAC2NNP9Qg8+ObU=8A AT mail DOT gmail DOT com>
Reply-To:	geda-user AT delorie DOT com

> Presumably this operates with "normal" nets and pins, not gschem buses -
> which still (as far as I recall) don't netlist.

Correct.

> One potential disadvantage of using this, (user choice of course), is that
> until more work on applying new semantic rules is done in geda, schematics
> using this new attribute semantics will be less easily reused for other
> work like simulation.

And verilog uses a different bus syntax, too.  It's up to the gnetlist
folks to decide if they want to "centralize" this, I'd much rather
have my backend call a function that says "please expand busses for
me" and be done with it.

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