Mail Archives: geda-user/2016/01/08/08:25:04
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| Date: | Fri, 08 Jan 2016 13:24:53 +0000
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| From: | "M. J. Everitt (m DOT j DOT everitt AT iee DOT org) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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| To: | geda-user AT delorie DOT com
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| Subject: | Re: [geda-user] first attempt at bus support in gnetlist for pcb
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| References: | <201601080714 DOT u087Ejj5032766 AT envy DOT delorie DOT com> <CAJXU7q8ebvSPZ-sYrTcSd+0qWeGs5ZEzQAC2NNP9Qg8+ObU=8A AT mail DOT gmail DOT com> <D098D4C9-0CB3-49F7-BD4C-C95874B99E44 AT noqsi DOT com>
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I propose filing a 'bug' or 'feature request' on one of the central
systems, so we can look at getting this completed and tested, if
everyone agrees? Can then link it to commits, etc ... merge, release!?!
MJE
On 08/01/16 12:38, John Doty wrote:
>
> On Jan 8, 2016, at 6:41 AM, Peter Clifton
> (petercjclifton AT googlemail DOT com <mailto:petercjclifton AT googlemail DOT com>)
> [via geda-user AT delorie DOT com <mailto:geda-user AT delorie DOT com>]
> <geda-user AT delorie DOT com <mailto:geda-user AT delorie DOT com>> wrote:
>
>>
>> On 8 Jan 2016 07:17, "DJ Delorie" <dj AT delorie DOT com
>> <mailto:dj AT delorie DOT com>> wrote:
>> >
>>
>> > The net result of this is that you can assign a net named
>> "nBL,A[8-2]" to
>> > a pin labelled "A[0-7]" and numbered "1-4,10-7" and they'll all get
>> > hooked up as appropriate.
>>
>> Presumably this operates with "normal" nets and pins, not gschem
>> buses - which still (as far as I recall) don't netlist.
>>
>> > You can also have a pin named "GND" and numbered "1,15,18" connected
>> > to net "GND" and it will connect all three pins to the one net.
>>
>> > Constructive feedback welcome!
>>
>> I think the solution you proposed looks useful and pragmatic.
>>
>> One potential disadvantage of using this, (user choice of course), is
>> that until more work on applying new semantic rules is done in geda,
>> schematics using this new attribute semantics will be less easily
>> reused for other work like simulation.
>>
>>
>
> You can do this kind of thing with a plug-in that wraps the
> appropriate gnetlist primitives. It’s somewhat harder, but could apply
> to most back ends, not just pcb.
>>
>> Regarding bus pins & buses vs. Net pins and nets.... I start to
>> wonder if we should aim to reduce that distinction in the future, and
>> make all nets / pins / buses more equally handled in gEDA. (Up to the
>> netlist backend / resolver).
>>
>>
>
> Yes. And then, erase the distinction between nets, busses, pins, and
> lines. Move that into attributes: a line with netname= is a net, a
> line with pinnumber= is a pin …
>
> This would let the user decide the appropriate line style for nets,
> busses, and pins. Keep the old method for backward compatibility, of
> course.
>>
>> Optional stronger port typing like VHDL / verilog would also be nice,
>> for schematics that drive hdl output.
>>
>>
>
> That kind of thing belongs in a DRC script, I think.
>>
>> Please can anyone replying consider whether a new thread is
>> appropriate if addressing my comments, not DJ's new feature.
>>
>> > DJ
>>
>
> John Doty Noqsi Aerospace, Ltd.
>
> http://www.noqsi.com/
>
> jpd AT noqsi DOT com <mailto:jpd AT noqsi DOT com>
>
>
>
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I propose filing a 'bug' or 'feature request' on one of the central
systems, so we can look at getting this completed and tested, if
everyone agrees? Can then link it to commits, etc ... merge,
release!?!<br>
<br>
MJE<br>
<br>
<div class="moz-cite-prefix">On 08/01/16 12:38, John Doty wrote:<br>
</div>
<blockquote
cite="mid:D098D4C9-0CB3-49F7-BD4C-C95874B99E44 AT noqsi DOT com"
type="cite">
<meta http-equiv="Content-Type" content="text/html;
charset=windows-1252">
<br>
<div>
<div>On Jan 8, 2016, at 6:41 AM, Peter Clifton (<a
moz-do-not-send="true"
href="mailto:petercjclifton AT googlemail DOT com">petercjclifton AT googlemail DOT com</a>)
[via <a moz-do-not-send="true"
href="mailto:geda-user AT delorie DOT com">geda-user AT delorie DOT com</a>]
<<a moz-do-not-send="true"
href="mailto:geda-user AT delorie DOT com">geda-user AT delorie DOT com</a>>
wrote:</div>
<br class="Apple-interchange-newline">
<blockquote type="cite">
<p dir="ltr"><br>
On 8 Jan 2016 07:17, "DJ Delorie" <<a
moz-do-not-send="true" href="mailto:dj AT delorie DOT com">dj AT delorie DOT com</a>>
wrote:<br>
><br>
</p>
<p dir="ltr">> The net result of this is that you can
assign a net named "nBL,A[8-2]" to<br>
> a pin labelled "A[0-7]" and numbered "1-4,10-7" and
they'll all get<br>
> hooked up as appropriate.</p>
<p dir="ltr">Presumably this operates with "normal" nets and
pins, not gschem buses - which still (as far as I recall)
don't netlist.</p>
<p dir="ltr">> You can also have a pin named "GND" and
numbered "1,15,18" connected<br>
> to net "GND" and it will connect all three pins to the
one net.</p>
<p dir="ltr">> Constructive feedback welcome!</p>
<p dir="ltr">I think the solution you proposed looks useful
and pragmatic.</p>
<p dir="ltr">One potential disadvantage of using this, (user
choice of course), is that until more work on applying new
semantic rules is done in geda, schematics using this new
attribute semantics will be less easily reused for other
work like simulation.</p>
<div><br>
</div>
</blockquote>
<div><br>
</div>
You can do this kind of thing with a plug-in that wraps the
appropriate gnetlist primitives. It’s somewhat harder, but could
apply to most back ends, not just pcb.<br>
<blockquote type="cite">
<p dir="ltr">Regarding bus pins & buses vs. Net pins and
nets.... I start to wonder if we should aim to reduce that
distinction in the future, and make all nets / pins / buses
more equally handled in gEDA. (Up to the netlist backend /
resolver).</p>
<div><br>
</div>
</blockquote>
<div><br>
</div>
Yes. And then, erase the distinction between nets, busses, pins,
and lines. Move that into attributes: a line with netname= is a
net, a line with pinnumber= is a pin …</div>
<div><br>
</div>
<div>This would let the user decide the appropriate line style for
nets, busses, and pins. Keep the old method for backward
compatibility, of course.<br>
<blockquote type="cite">
<p dir="ltr">Optional stronger port typing like VHDL / verilog
would also be nice, for schematics that drive hdl output.</p>
<div><br>
</div>
</blockquote>
<div><br>
</div>
That kind of thing belongs in a DRC script, I think.<br>
<blockquote type="cite">
<p dir="ltr">Please can anyone replying consider whether a new
thread is appropriate if addressing my comments, not DJ's
new feature.<br>
<br>
</p>
<p dir="ltr">> DJ<br>
</p>
</blockquote>
</div>
<br>
<div apple-content-edited="true">
<span class="Apple-style-span" style="border-collapse: separate;
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<p style="margin: 0.0px 0.0px 0.0px 0.0px"><font style="font:
12.0px Helvetica" size="3" face="Helvetica">John Doty<span
class="Apple-converted-space"> <span
class="Apple-converted-space"> </span><span
class="Apple-converted-tab"> <span
class="Apple-converted-space"> </span></span></span>Noqsi
Aerospace, Ltd.</font></p>
<p style="margin: 0.0px 0.0px 0.0px 0.0px"><a
moz-do-not-send="true" href="http://www.noqsi.com/">http://www.noqsi.com/</a></p>
<p style="margin: 0.0px 0.0px 0.0px 0.0px"><font style="font:
12.0px Helvetica" size="3" face="Helvetica"><a
moz-do-not-send="true" href="mailto:jpd AT noqsi DOT com">jpd AT noqsi DOT com</a></font></p>
<br class="Apple-interchange-newline">
</span>
</div>
<br>
</blockquote>
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