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"Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> writes: > Indeed, although it realistically isn't actally that huge a task from the > data point of view. The most obvious missing thing I can see, is a physical > layer stack model. Pcb layers don't explicitly map 1-1 to physical layers - > and at the very least, we need to inforce a defined ordering of layer > groups, before a to-from layer group notion makes sense. (I sort of did > this in the 3D branch, but it needs to be more explicit). I do not agree that we need a 3D physical model in PCB. That would be a different tool. PCB as is describes abstract elements of a printed cicuit. A Via needs to tell which layers/groups it connects to, and what kind of pads there are on those layers. It may be nice if the file format ensures that the layout can be implemented on a pcb. And that requires to define a layer order and restrict vias to continuous sets of layers. But who knows. Maybe that is a restriction that some day prevents some use for somebody? Maybe it is up to the DRC check to verify that there are no unphysical vias. Layer order becomes a part of the design rules. If the user can choose vias from a library of known good vias, that will not be a problem. The distinction between Pin and Pad can be removed. A Pad is a Via inside an Element with only one layer and no hole. No Via connects to an outline layer or a documentation layer, no more need for a rule/script in the Makefile to remove Pins and Vias from a layout to export documentation layers. Currently, all my PCB files to not have the layers in physical order. I like to have at least top and bottom layers always in the same colors, so those are on layers 0 and 3, no matter how many layers the board shall have, which may not be known from the start. -- Stephan
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