X-Authentication-Warning:	delorie.com: mail set sender to geda-user-bounces using -f
X-Recipient:	geda-user AT delorie DOT com
X-Original-DKIM-Signature:	v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=googlemail.com; s=20120113;
	h=mime-version:in-reply-to:references:date:message-id:subject:from:to
	:content-type;
	bh=pjsHANWSUUahR+94fISZcdauQSfradVOqtXHao5tbNc=;
	b=dGw2kx1eUXkAHHlC33Mkfa7sTZNKyG0cVS49aunRIfyZYByDhpW2N51JHN8D52j0WU
	Rh31NMznvpU+2LIdGS/370V51s/He1x6Ka5EbbPHaIkuDSO+ZrGiTONmyMHK/SqB7M26
	Pu7Xc8DQf7CSXEEaCMq40Xf9jEuU+Kn8WXAEX5yPSd98d8AMhQIwIyTMWiFTOtfIRNN+
	NFLmnA/oeCRWFABgH9AfWUm60u7PaZ2MhWzdRh1mFI46x+tdVaJwl0k6yGBUg3GhC6fk
	urfOXLH3ranB3pUPBQupWpYt/7zIzH+Imv0KTD9y+5dm5ptao9K/JS/qGcw4Ft/zhsvb
	ZIFg==
MIME-Version:	1.0
X-Received:	by 10.202.213.215 with SMTP id m206mr59484816oig.26.1451916768922;
	Mon, 04 Jan 2016 06:12:48 -0800 (PST)
In-Reply-To:	<alpine.DEB.2.11.1601010135550.2280@newt>
References:	<5AC3D5C5-144F-41AE-9562-47BC34D9047F AT noqsi DOT com>
	<CAJXU7q_GnuGNMtUWkB-xgBiKgY5R5W4ZCjtnz5EJizG+46dm1w AT mail DOT gmail DOT com>
	<C7FDF8B6-B335-46C3-8A25-F95ACECF4B79 AT noqsi DOT com>
	<CAJXU7q_3XwthnN_8mp7B+-ShHeK+=7J=54ZavKBUG3S3bSKp2A AT mail DOT gmail DOT com>
	<20151222193859 DOT 26898 DOT qmail AT stuge DOT se>
	<20151223202851 DOT 637d5b1f AT jive DOT levalinux DOT org>
	<20151223195846 DOT 8392 DOT qmail AT stuge DOT se>
	<CAM2RGhS2bg=Rjuq6oEeOacV7PfUENy_jq7dxag=vWsUbdH6pAQ AT mail DOT gmail DOT com>
	<20151229155647 DOT GA3752 AT localhost DOT localdomain>
	<CAM2RGhSLND5+JSSj=1cUPUhzkTCK6d7NZ61QL-eViZRccY5LqA AT mail DOT gmail DOT com>
	<20151229175222 DOT GD3752 AT localhost DOT localdomain>
	<alpine DOT DEB DOT 2 DOT 11 DOT 1512311656190 DOT 1475 AT newt>
	<96A12FC1-E09C-4D63-8346-5A62FDAB4228 AT sbcglobal DOT net>
	<alpine DOT DEB DOT 2 DOT 11 DOT 1512311916190 DOT 12724 AT newt>
	<2F0AFAE8-ADAB-4DE0-A79C-DD87077E66B5 AT sbcglobal DOT net>
	<alpine DOT DEB DOT 2 DOT 11 DOT 1601010135550 DOT 2280 AT newt>
Date:	Mon, 4 Jan 2016 14:12:48 +0000
Message-ID:	<CAJXU7q_H54n7-iyephsGF8DnSvu2f1zv_jqkFsthDwVCVa7BnQ@mail.gmail.com>
Subject:	Re: [geda-user] Project leadership
From:	"Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To:	gEDA User Mailing List <geda-user AT delorie DOT com>
Reply-To:	geda-user AT delorie DOT com
Errors-To:	nobody AT delorie DOT com
X-Mailing-List:	geda-user AT delorie DOT com
X-Unsubscribes-To:	listserv AT delorie DOT com

--001a113de56841530b052882b777
Content-Type: text/plain; charset=UTF-8

On 4 Jan 2016 14:00, "Roland Lutz" <rlutz AT hedmen DOT org> wrote:

> Thinking about it, I'm not even sure if this behavior (treating the slots
of a package as individual SPICE objects) is even necessary.  The other
SPICE backends don't seem to be using it.

An alternative option would be to have a (schematic or netlist based)
sub-model which maps the connections of the actual part, to 'n' internal
instances of the cell model.

It really depends on whether you are viewing the schematic and spice
simulation as that of the design with actual parts, or at a more abstracted
level where actual embodiment of the opamp cells means picking what chip
they go in.

At a detailed level, the physical model can include more parasitics at
physically representitive points in the model.

Seems similar in some way to the differences between simulating your VHDL /
verilog as written (perhaps with timing back annotated), vs. simulating the
synthesised netlist.

Usually we don't have a synthesize or map step in the schematic to pcb
workflow of course!

Peter

--001a113de56841530b052882b777
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable

<p dir=3D"ltr"><br>
On 4 Jan 2016 14:00, &quot;Roland Lutz&quot; &lt;<a href=3D"mailto:rlutz AT he=
dmen.org">rlutz AT hedmen DOT org</a>&gt; wrote:</p>
<p dir=3D"ltr">&gt; Thinking about it, I&#39;m not even sure if this behavi=
or (treating the slots of a package as individual SPICE objects) is even ne=
cessary.=C2=A0 The other SPICE backends don&#39;t seem to be using it.<br><=
/p>
<p dir=3D"ltr">An alternative option would be to have a (schematic or netli=
st based) sub-model which maps the connections of the actual part, to &#39;=
n&#39; internal instances of the cell model.</p>
<p dir=3D"ltr">It really depends on whether you are viewing the schematic a=
nd spice simulation as that of the design with actual parts, or at a more a=
bstracted level where actual embodiment of the opamp cells means picking wh=
at chip they go in.</p>
<p dir=3D"ltr">At a detailed level, the physical model can include more par=
asitics at physically representitive points in the model.</p>
<p dir=3D"ltr">Seems similar in some way to the differences between simulat=
ing your VHDL / verilog as written (perhaps with timing back annotated), vs=
. simulating the synthesised netlist.</p>
<p dir=3D"ltr">Usually we don&#39;t have a synthesize or map step in the sc=
hematic to pcb workflow of course!</p>
<p dir=3D"ltr">Peter</p>

--001a113de56841530b052882b777--

- Raw text -